Ghodssi R., Lin P., MEMS Materials and Processes Handbook
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824 S.J. Cunningham a nd M. Kupnik
Attractive forceRepulsive force
Force
Separation
~ 0.2 nm
~ 1 nm
~ 0.4 nm
Fig. 11.3 Typical
force-separation curve valid
for van der Waals forces
between two surfaces. In
terms of the given numbers,
this curve is only valid for
van der Waals forces; that is,
the effect of hydrogen bonds
is neglected. See, for
example, [11–13]
11.2.2 Parameters for Successful Direct Wafer Bonding
The concept of work of adhesion provides a basic understanding of the parameters
one needs to focus on during the development of a MEMS process that requires
direct wafer bonding. The goal of this section is to provide a guideline for the
development of a MEMS fabrication process that contains a direct wafer bonding
step.
Before further discussing all relevant parameters for such a guideline, we define
important topographical parameters of wafers in general. As Turner [11] describes in
his thesis, three different flatness deviations may be loosely defined for that purpose
(Fig. 11.4), which are based on their spatial wavelengths.
< 100 nm
< 10 nm
(a) (b) (c)
Roughness Waviness Wafer shape
0.1 – 20 mm
10 – 100 nm
100 – 300 mm
10 – 200 um
Fig. 11.4 Typical types of flatness variations on typical wafer, after [11]
11.2.2.1 Surface Roughness
The flatness variation with the smallest spatial wavelength is described by roughness
parameters (Fig. 11.4, leftmost) such as the root-mean-square (RMS) value of the
roughness depth. This important parameter is calculated by taking the root mean
square of the series of measurements of deviations from the centerline. The best
tool for carrying out such measurements is an atomic force microscope (AFM) [14].
Having access to an AFM for the development of a MEMS fabrication process that
includes a direct wafer bonding step is invaluable. The AFM enables checking the
wafer s urface for the presence of particles and it delivers the surface roughness
11 Wafer Bonding 825
(a) (b)
(c) (d)
3.5 nm RMS
0.18 nm RMS0.18 nm RMS
Fig. 11.5 Atomic force microscope measurements of three different samples: (a) wafer contam-
inated with particles; (b) silicon wafer with rough surface (has been exposed to plasma), which
would fail to bond via direct wafer bonding; (c) fresh prime quality wafer with smooth surface; (d)
rescaled (z-axis) view of the same data from (c). These wafers direct bonded successfully. For all
three samples an area of 5 × 5 μm was scanned
information directly as a first indication of whether this wafer can be direct bonded.
Figure 11.5 shows exemplary results of such AFM measurements for three different
silicon samples.
On the first sample (Fig. 11.5a), five particles have been detected by the AFM.
The grooves, before and after each particle, are related to the dynamics of the AFM
cantilever and can be ignored for this context. Because for all of these measurements
only a small area of 5 × 5 μm was scanned, this wafer can be assumed heavily
contaminated by particles, and, thus, requires proper cleaning (see Section 11.2.4.1)
prior to direct wafer bonding.
The second measurement result (Fig. 11.5b) is from a silicon wafer that was
exposed to a plasma-etching tool (resist removal tool). The surface roughness is
significantly larger than from the fresh prime quality silicon wafer (Fig. 11.5c, d).
These two samples were used for direct wafer bonding tests. The intentionally
roughened wafer did not bond and the smooth wafer bonded well.
The roughness of the surface is an important parameter, but it is not the only
one, as we show later. Therefore, only a quantitative upper limit of the RMS sur-
face roughness number for the direct “bondability” of a wafer can be given as a
826 S.J. Cunningham a nd M. Kupnik
guideline. This limit is around 0.25 and 0.5 nm for hydrophobic
2
and hydrophilic
silicon wafers, respectively. These numbers are based on our own experiments and
reported in the literature; see, for example, [8].
11.2.2.2 Waviness or Nanotopography
The waviness or nanotopography is f ound on a scale about three orders of magni-
tude larger than roughness (Fig. 11.4, center). In addition to AFM measurements
over a larger scan area, a good indicator of the wafer quality is the total thickness
variation (TTV), because it quantifies the wafer topography on that range of spatial
wavelength as well. It is defined as the maximal height difference between the high-
est and lowest elevation of the top surface of the wafer. Off-the-shelf prime grade
wafers exhibit TTV values of around 2 μm.
11.2.2.3 Wafer Shape
The wafer shape has the largest s patial wavelength and reflects the radius of cur-
vature and warp of the wafer. Direct wafer bonding in particular requires that both
wafers merge into the exact same curvature state, which requires energy to over-
come the strain energy present in the wafers before the bond. Note that depending
on the fabrication steps before the bonding step, the wafers can be flat, concave, or
convex. Certainly, the worst-case scenario is the situation where a concave and a
convex wafer are supposed to be direct bonded. The bond wave will only advance,
as it does in Fig. 11.2, when the surface energies for the nonbonded area are large
enough to overcome the strain per unit area [11]. As example, Fig. 11.4 (rightmost)
shows a concave wafer shape. Such a shape can be due to a compressive layer, such
as a thick thermally grown silicon dioxide layer on the backside, for example.
11.2.3 Recommendations for Successful Direct Wafer Bonding
As mentioned at the beginning of this section, our goal is to provide a guideline
with recommendations for those parameters one needs to focus on while planning a
MEMS fabrication process that utilizes a direct wafer bonding step:
• Ensure a particle-free bonding surface, that is, a clean environment. This is
absolutely necessary for a good bonding yield.
• Protect the bonding surface during all fabrication steps prior to direct wafer
bonding. Any exposure of the bonding area to plasma or liquid etchants must
be avoided or minimized to the absolute minimum. For example, Miki and
2
A hydrophobic (in Greek hydro means water and phobos means fear) surface is characterized by
a high contact angle of water on that surface; that is, a hydrophobic surface has a low wettability.
Hydrophilic (in Greek philia means friendship) surfaces have low contact angle of water, that is,
high wettability.
11 Wafer Bonding 827
Spearing [15] investigated the effect of buffered oxide etch (BOE) and/or potas-
sium hydroxide solutions (KOH) on the surface roughness of silicon wafers.
Their experiments showed a clear decline of the effective work of adhesion
(bond energy) with the BOE and/or KOH treatment time due to increased sur-
face roughness. The immediate conclusion is that too long an overetch during a
silicon dioxide strip step, using BOE, can prevent successful direct wafer bond-
ing. Without proper AFM measurements such an increase in surface roughness
would stay undiscovered.
The protection of the bonding surface can be achieved with different tech-
niques, such as by using photoresist, thermally grown oxide, silicon nitride, or
other protective layers. This ensures low surface roughness values, assuming
the layer can be removed after certain fabrication s teps without harming the
wafer surface. This is also valid for removing photoresist. Instead of using a
plasma-based resist-removing tool (ashes the resist by heat), as commonly found
in MEMS and CMOS foundries, one should rather use a regular piranha solu-
tion (H
2
O
2
:H
2
SO
4
) for removing the photoresist to avoid any extensive plasma
exposure of the wafer surface. Maintaining a low surface roughness is purely
motivated by the goal to maximize the available work of adhesion. The larger the
free surface energies, the more energy is available to overcome the strain in the
wafers. Based on this observation more recommendations can be given.
• Keep the wafers as flat as possible before the direct wafer bonding step in terms of
their radius of curvature. In case you have a MEMS process that includes several
fabrication steps before bonding, such as DRIE of cavities and/or the deposi-
tion of tensile or compressive films, try to monitor the radius of curvature of the
wafer. The exact knowledge of these changes in curvature allows planning steps
for stress state compensation of the wafer. For example, a MEMS fabrication pro-
cess requires an etch step (DRIE), but also the thermal growing of thick silicon
dioxide, for electrical insulation. By monitoring the curvature of the wafer, we
can selectively reduce the thickness of the compressive oxide on the backside
with the goal of reducing the radius of curvature before the direct bonding step.
This minimizes the required energy to overcome the strain energy present in the
wafers before the bond, and, this increases the likelihood of a successful direct
bond with good yield.
• In addition, avoid using thick wafers when not required in your MEMS process.
Where you have the choice between thicker and thinner substrates, choose the
thinner one. For example, in the fabrication process of a MEMS device a direct
wafer bonding step is required for transferring the active layer of an SOI wafer.
After that transfer the handle and buried oxide layer (BOX) need to be removed.
In this case it is better to order the SOI wafer with a thinner handle wafer and
with a thinner BOX layer when possible. This makes it easier to perform the
direct wafer bonding step, because there is less energy required to overcome the
strain in the wafers. The reduced energy to deform thin wafers is because the
stiffness of the wafer scales to the cubic power of thickness (αt
3
), which means if
the wafer thickness is reduced by a factor of 2 the stiffness is reduced by a factor
of 8. This is a very advantageous scaling for bonding.
828 S.J. Cunningham a nd M. Kupnik
• The overall integration of your MEMS process should consider a proper surface
activation method. This again has the goal of maximizing the available free sur-
face energies. There are several choices available, such as chemical-assisted and
plasma-assisted activation (see Section 11.2.4.1).
• While planning the layout of your MEMS fabrication process, keep the propa-
gation of the bonding wave in mind. Basically all wafer bonding tools initiate
the first contact between the two wafers in the center and then apply a defined
force on the wafer stack to support the bonding step. Before the tool applies the
force, the bonding wave propagates fairly symmetrical to the outside, as visible
in Fig. 11.2. In case your MEMS fabrication process contains an etch step before
the direct wafer bonding step for things such as fluid channels or cavities, the etch
pattern plays a significant role. A larger bonding area will provide more free sur-
face energy for the bond. Hence, for the same curvature and roughness situation,
it will always be easier to bond a nonpatterned wafer or a wafer with a pattern
that provides more bonding area. In addition, a good layout choice that supports
stable bond wave propagation might be helpful as well. Such a pattern could be
a spoke pattern, that is, a bonding area between the MEMS devices that provides
continuing outwardly radial stripes, as investigated by [11] in great detail.
11.2.4 Procedure of Direct Wafer Bonding
This section gives a detailed overview of how wafers are direct bonded. The struc-
ture of the section is based on Fig. 11.6, which outlines how a direct wafer bonding
step is embedded in a MEMS fabrication process.
11.2.4.1 Surface Preparation for Direct Wafer Bonding
Planarization Step
Sometimes the bonding criteria, as described in the previous section, are fulfilled
and one does not need to polish the wafer surface by chemical mechanical polish-
ing (CMP) to achieve the surface smoothness required for direct wafer bonding.
However, for many MEMS devices, CMP is required to obtain a sufficiently smooth
and flat surface. In addition, CMP can also be seen as a cleaning step because it
can be used to remove the uppermost layer of material (few nanometers) and, thus,
eliminating all surface contaminants present on the surface. For wafers with etched
patterns or other surface topography, CMP can be challenging due to dishing and
erosion effects [8, 16]. In addition to silicon and thermally grown silicon dioxide,
CMP enables preparation of many other commonly used materials in MEMS pro-
cesses for direct wafer bonding, such as polycrystalline silicon, low-temperature
oxide (LTO), tetraethoxysilane (TEOS) (low stress) silicon nitride, silicon carbide,
quartz, fused silica, aluminum oxide, certain types of polymers, and even nanocrys-
talline diamond films. Based on our own experience, we can recommend for such
cases to consult with a highly specialized CMP company, such as Entrepix, Inc.,
Tempe, AZ, CTO Dr. Robert Rhoades.
11 Wafer Bonding 829
Conditions for direct wafer
lled
Alignment required, vacuum or
c ambient required, many
wafers, individual temperature during
bond (top vs. bottom wafer) ?
Yes
No
Yes
No
Yes
No
Polish wafers (CMP) and/ or
reduce curvature if possible
Fabrication steps of MEMS process
before direct bonding
Clean surface (RCA), HF dip only in case
hydrophobic surface is needed
Surface Activation:
- Chemical
- Plasma assisted
- Laser assisted (in tool)
Bond at room temperature/
elevated (hot plate),
done by hand
Bonding/Alignment tool
needed, at room/elevated
temperature
Thermal treatment according thermal budget
- high temperature fusion step
- low temperature fusion step
- no further heat treatment
Inspect wafers (e.g. IR) to check
for (particle) voids. Ok ?
Continue with MEMS fabrication
Fig. 11.6 Quantitative overview of how a direct wafer bonding step can be seen embedded in
a MEMS fabrication process. Depending on the t ype of MEMS device there are several options
available
830 S.J. Cunningham a nd M. Kupnik
Cleaning of Wafer Surface
After the wafers are in the state of having a smooth surface, careful cleaning
is required. The surface of the wafers for a direct wafer bonding step requires
extra careful cleaning. The goal is to have no particle contamination, no organic
contamination (hydrocarbons from air, commonly found in high concentrations
in cleanroom environments), and no ionic contamination (from metal tweezers,
glassware, etc.).
The effect of these three types of contamination in terms of bonding is different
[8].
Particles on the surface, such as shown in Fig. 11.5, have the most severe influ-
ence on direct wafer bonding. They act as spacers and produce a separation. As a
rule of thumb, a 1 μmlargeparticleona4in.silicon wafer produces a void of
about 1 cm in diameter [8]. As shown in Fig. 11.6, particle-induced voids can be
detected by simple IR inspection after the room temperature bond has been per-
formed. Because at that stage the bond is reversible, the wafers can be separated
and cleaned again. In the case where the particle void is ignored or too small for IR
detection (the large wavelength of the IR source limits the resolution), the size of
the void will only reduce slightly during the subsequent annealing step and, thus,
reduce the yield.
In terms of organic contamination the main problem is that the quality of
adhesion becomes degraded. After the room temperature bonding step, usually
nonbonded areas do not occur or at least are not large enough to be detected by
IR, but then during the thermal treatment step, thermally induced voids can occur
(nucleation of interface bubbles).
The concerns of metallic contamination are not so much on the quality of the
direct bond itself, but on the electronic properties of the semiconductor material,
which often might not be a problem at all for MEMS devices.
In general, the cleaning step for direct wafer bonding is not different than stan-
dard cleaning procedures [17, 18] in the microelectronics industry. A standard
hydrogen peroxide-based RCA1
3
wet cleaning procedure (mixture of ammonium
hydroxide, hydrogen peroxide, and DI water, in ratio 1:1:5) can be used, fol-
lowed by an RCA2 clean (mixture of hydrochloric acid, hydrogen peroxide, and
DI water). Another alternative, which the authors of this chapter use at the Stanford
Nanofabrication Facility, is to use a hydrogen peroxide and sulfuric acid (piranha
clean) mixture instead of the RCA1, followed by a standard RCA2 step. No increase
in surface roughness has been found (surface roughness measurements by AFM)
after this cleaning procedure, even after extensive cleaning times.
As indicated in Fig. 11.6, a dip in hydrofluoric acid (HF) can be included in the
cleaning sequence. In the case of a silicon wafer this would create a hydrophobic
surface because the native oxide is removed. Using this HF dip usually is advan-
tageous, because the native oxide layer often acts as a trap for metallic or organic
contaminations. It does not prevent the option of performing a hydrophilic bond,
3
Named after the company Radio Corporation of America (RCA), in which Werner Kern, the
developer of this cleaning procedure, was working at that time [17].
11 Wafer Bonding 831
because it depends on the type of surface activation step, whether a hydrophobic or
hydrophilic direct bond is made.
Activation of Wafer Surface
For direct wafer bonding the surface activation step after the wafer cleaning is prob-
ably the most important step. The goal is twofold: to maximize the available free
surface energy and to terminate the wafer surface, that is, the dangling bonds, which
would be very reactive in the case where the wafers need to be exposed to cleanroom
air before the direct bonding step can be performed.
As mentioned in the previous section, there is often the important choice of
whether the direct bonding should be performed with a hydrophobic or hydrophilic
surface. Several aspects should be considered for the decision of whether a
hydrophobic or hydrophilic surface is used. These aspects are discussed as follows
for the example of silicon wafers:
• Two silicon wafers can be direct bonded with hydrophobic surfaces by strip-
ping the native oxide right before the bonding step by means of, for example,
performing an HF dip. In this case the bonding surface provides good electrical
connection as well. However, as soon as the bare silicon surface comes in con-
tact with any oxygen-providing ambient (also from the cleaning solutions used
for the RCA clean, as discussed before), a fresh native oxide layer will grow,
and, thus, the surfaces will be hydrophilic. The same is the case for wafers with
intentionally grown oxide films, but only when there is enough time and water
available for sufficient hydration of the oxide film. Such oxide film will be rela-
tively dehydrated, in particular right after oxidation in a dry ambient, and, thus,
be hydrophobic.
• Another aspect concerns the available thermal budget for the heat treatment step,
that is, the maximum temperature the wafers can handle. In this context, the
choice between hydrophobic versus hydrophilic bonding surfaces is essential
because it affects the bond mechanism for both the room temperature bonding, as
well as the reactions during the heat treatment step with the danger of increased
void formation (interface bubbles). This is discussed in Section 11.2.4.4 in more
detail.
• For hydrophobic silicon surfaces the dangling bonds are terminated by hydrogen
and fluorine depending on the ambient conditions, except in bonding tools where
the native oxide is removed under vacuum condition (see Section 11.8.2 about
wafer bonding tool vendors for details). The dangling bonds of the hydrophilic
silicon surface are terminated by oxygen–hydrogen (OH) groups (silanol groups).
The free surface energy of this OH-terminated surface is significantly higher ∼5
times due to hydrogen bonds [8], which, in general, is the reason why it is more
difficult to initiate a direct bond with hydrophobic than with hydrophilic silicon
wafers.
Thus, in general, a surface activation that leads to hydrophilic surfaces is
preferred and commonly used for direct wafer bonding.
832 S.J. Cunningham a nd M. Kupnik
The activation for a hydrophilic surface can be performed by chemical activation,
that is, by simply immersing the wafers into an ammonium hydroxide solution, sim-
ilar as RCA1, at around 75
◦
C for 15 min, as described, for example, in [19]. Another
approach for effective hydrophilization is using oxygen plasma [20]. For example,
[19] uses a 100 W, 6 sccm oxygen gas plasma in a reactive ion etcher with a base
pressure of 15 mtorr for a duration of 10 s and reports significantly improved bond-
ing strengths, even after low-temperature annealing (∼300
◦
C). For both activation
methods (i.e., chemical and plasma) the goal is to have a high density of OH groups
on the bonding surfaces.
When one direct bonds two wafers that have thicker films than just native oxide,
special care must be taken. Even after a long heat treatment at high temperatures
(>1000
◦
C) after the bond, the silicon dioxide to silicon dioxide bonding interface
can be a significant weak point in the stack for the remaining fabrication steps in
the MEMS device and, thus, should be avoided if possible. Köhler et al. [21]inves-
tigated this for liquid HF, which produces significant damage at the oxide–oxide
bond interface. These authors report that the bond interface of silicon dioxide to sil-
icon dioxide is heavily attacked by liquid HF due to capillary forces at the interface,
which can form a void between the two silicon wafers and weaken the structure
(high stress point). This is not the case for silicon-to-silicon and silicon-to-silicon
dioxide bonding interfaces. Furthermore, for the grown interface between silicon
and silicon dioxide no such damage can be observed.
Even more dramatic is the effect when vapor HF is used, which is commonly used
in MEMS fabrication processes as well. We conducted the following experiment to
demonstrate how the silicon dioxide to silicon dioxide bonding interface is attacked
by HF vapor. We oxidized two silicon wafers (2.5 μm, wet ambient at 1100
◦
C) and
then performed a direct bond (chemically activated as described before, and thermal
treatment at 1100
◦
C for 4 h). After etching (DRIE) trenches into the silicon wafers
from one side, we exposed the silicon dioxide to HF vapor. The wafer was kept at
45
◦
C during this HF vapor etching step to avoid condensation. The first 2.5 μm
oxide were etched with an etch rate of ∼100 nm per minute, as expected. As soon
as the oxide-to-oxide bonding interface was reached by the HF vapor, the interface
was severely attacked (Fig. 11.7a). At the bonding interface, the horizontal etch rate
increased by a factor of ∼250 (!) (Fig. 11.7b). It seems that imperfections along the
oxide–oxide bonding interface in combination with capillary forces are responsible
for this high anisotropic etch rate. However, for intentional release steps of large
structures this can be advantageous. In the case where the oxide–oxide interface is
exposed to plasma etching, no such behavior can be observed. In addition, the same
experiment, repeated for a silicon-to-silicon oxide bonding interface, reveals that no
horizontal etch rate increase occurs.
11.2.4.2 Bonding Step – By Hand or by Using a Wafer Bonding Tool
The next decision one has to make (Fig. 11.6) depends on the type of MEMS device
that is fabricated. As previously shown in Fig. 11.2, two wafers can be direct bonded
11 Wafer Bonding 833
(a)
(b)
Silicon
Silicon
Oxide remaining
Location of bonding
interface before etch
~ 250 micron etched in 10 min
Fig. 11.7 SEMs showing that a direct bonded silicon dioxide-to-silicon dioxide bonding interface
is very vulnerable when exposed to HF vapor
by just putting them on top of each other and gently applying some force at the cen-
ter location. Then this wafer stack can be loaded in a furnace, on top of a hot plate, or
beneath an IR lamp to strengthen the bond. Therefore, in principle no complicated
bonding tool is required for the bonding step itself. A good example f or such a case
is the device described by Sarioglu and Solgaard [22]. This novel AFM cantilever
was fabricated based on a direct wafer bonding step: first the room temperature bond
was performed by hand with the help of a tilted support block made of Teflon (poly-
tetrafluoroethylene, hand-bonding tool; see Fig. 11.8) and then the wafer stack was
heated up in a regular oxidation furnace to 1050
◦
C for 2 h to strengthen the bond.
This hand-bonding tool allows submillimeter wafer level alignment for the bond-
ing and it is used as follows. The first wafer is placed on top of the block, and one
of the flats can be aligned to one of the edges on the left side (depends on the wafer
type and location of flats). The groove on the left side provides a well-defined edge
so that the wafer alignment is improved and it collects particles. Then the second
wafer is positioned on top of the first wafer. It will float on an air cushion, which
aligns the two wafers automatically by gravity due to the tilt. Then the pin (right)
is used to apply some force at the center location of the wafer stack, which initiates
the propagation of the bonding wave.
The best results are obtained when the bonding is performed below a flow bench
(fewer particles) or even better at an oxidation furnace, because then the airflow
direction is towards the operator. The tool is heavily used for direct wafer bonding