Ghodssi R., Lin P., MEMS Materials and Processes Handbook

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804 A.D. Raisanen

Solid-phase epitaxy

Thermal budget • Generally 500–700

◦

Time • Depends on thickness of amorphized layer

• Regrowth rates of 10–100 Å/min are typical at temperatures near 600

◦

C[7]

• Temperature ramp rate of furnaces also increases process time

• Typically 1 h or more

Material

compatibility

• Silicon

• SiO

• Si

• Some refractory metals/silicides

Disadvantages • Requires amorphous layer, so applicable only to ion implant processes

• Requires high ion doses or heavy ions to produce amorphous layer

Rapid thermal anneal

Thermal budget • Typically >700

◦

C for silicide anneals

• 900–1200

◦

C for dopant anneals

Time • Very fast, tens of seconds to minutes

• Flash lamp assist can be very fast, tens of milliseconds [78]

Material

compatibility

• Silicon

• SiO

• Si

(delamination due to stress in nitrides can be a serious issue)

• Some refractory metals/silicides

Disadvantages • Single wafer process; low throughput

• Temperature measurement difﬁcult, generally requires accurate optical

model of substrate emission for pyrometer [76]

• Dislocation formation possible i n crystals due to thermal nonuniformities

Laser anneal

Thermal budget • Effectively room temperature for the bulk of the substrate, although a

narrow region at the surface will reach high temperature for a short time

Time • Each point of the surface reaches high temperature for a very short time

(<1 s), but scanning the entire wafer can take several minutes

Material

compatibility

• Only the surface scanned by the laser is heated, so a variety of thermally

sensitive materials (metals, polymers, etc.) can exist elsewhere on the wafer

• Scanned region must be resistant to ablation or vaporization (standard Si,

SiO

,Si

refractories)

• Ideal for substrate materials with large thermal expansion coefﬁcient

mismatches

Disadvantages • Single wafer process; low throughput

• Scanning process lowers throughput even further

10.7.5 Case Study: Rapid Thermal Anneal Versus Conventional

Thermal Anneal

A university research project silicon substrate diode design (Fig. 10.39) required a

shallow but heavily doped boron implant, 1×10

boron/cm

with less than 0.5 μm

junction depth. We suspected that conventional diffusion tube annealing would

cause excessive diffusion and an unacceptably large junction depth. ATHENA simu-

lation of a 1 h 1100

◦

C thermal anneal process predicted a junction depth exceeding

10 Doping Processes for MEMS 805

Fig. 10.39 RTP versus thermal anneal for a boron implant. Data markers are spreading resis-

tance results; solid lines are simulations from ATHENA using Dual Pearson implant model. Data

courtesy of Professor Karl Hirschman at Rochester Institute of Technology

2 μm. A rapid thermal anneal lasting 60 s was chosen in hopes of achieving the

desired shallow junction.

Two experiments were performed for comparison purposes, the 1 h conventional

anneal at 1100

◦

C, and the 1 min rapid thermal anneal at 1100

◦

C. A screening

oxide layer of 300 Å of thermal SiO

was grown on the lightly P-doped n-type

silicon (100) wafers prior to implant to suppress boron channeling effects in the sil-

icon. Implants were performed on a Varian 350D medium-current implanter using

B11

ions at 40 keV energy. The wafers were annealed and the screening oxide

was stripped in hydroﬂuoric acid. Both wafers were sent to Solecon Laboratories in

Reno, NV for spreading resistance characterization.

Final spreading resistance proﬁles are in reasonable agreement with ATHENA

simulations. The rapid thermal anneal junction depth stayed at 0.5 μm, whereas the

conventionally annealed junction depth was found to be just over 2 μm.

10.8 Diagnostics

Analysis of doped layers is generally focused on extracting process parameters such

as dopant density, junction depth, and degree of electrical activation. Some param-

eters can be conveniently extracted nondestructively from wafers in midprocess,

but most require destructive analysis of a completed device. Electrical measure-

ments are convenient, inexpensive, and generally nondestructive, making them well

suited for statistical process control and routine characterization of junctions and

806 A.D. Raisanen

doping levels. Spreading resistance and surface analytical techniques provide sub-

stantially more information than electrical measurements, but are much slower and

considerably more expensive.

10.8.1 Electrical Measurements

Electrical resistivity measurements are by far the most common and straightforward

analytical techniques available for characterizing doped layers and ﬁlms. This class

of diagnostic test can generally be accomplished with very modest test equipment

found in many semiconductor laboratories, and fully automated four-point probe

wafer mapping systems are commercially available.

Four-point probe instrumentation (Fig. 10.40) is a convenient method of nonde-

structively verifying target resistivity of a doped layer. It can be conveniently used

on completed device structures or on partially completed layers in midprocess. Four

probe points, usually made of a tungsten carbide or other hard conductive material

for durability, are arranged in a line with equal spacing d between probes. A small

current I is forced across the two outer probe tips, and a potential V is measured

across the inner two probe tips. The sheet resistance is then given by

× C.F., (10.7)

where C.F. is a correction factor determined by the geometry of the measurement. In

practice, current values are typically chosen to produce voltage drops on the order

of 10 mV.

Fig. 10.40 Four-point probe

apparatus for measurement of

sheet resistances

For samples that are large relative to the interprobe spacing d, the correction

factor converges to the value for an inﬁnite plane, which is 4.53. This is the most

common geometrical arrangement when working with silicon wafers, but correction

factors are tabulated f or other circular geometries in Swartzendruber [82] and can be

calculated for arbitrary sizes and shapes of sample via Smits [83]. Sheet resistance

10 Doping Processes for MEMS 807

is expressed in ohms per square (/square), a hybrid unit that essentially assumes

a constant layer thickness when comparing measurements. If the thickness θ of the

doped layer is known by some other measurement method, the bulk resistivity in 

cm can be easily determined by

ρ = R

× θ . (10.8)

Four-point probe resistance measurements are a convolution of junction/thin

ﬁlm depth and resistivity, so are most useful in cases where the ﬁlm thickness is

accurately known (such as a deposited layer) or where the technique is being used

as an inline warning of processing anomalies. If the expected sheet resistance (from

previous measurements or by process modeling predictions) is not obtained, more

complex analyses can then be performed to discover the origin of the discrepancy.

Spreading resistance measurement techniques are signiﬁcantly more revealing

than simple four-point probe measurements, as both layer depth and resistivity are

extracted simultaneously. Doping type (n or p) can also be extracted in most cases.

Spreading resistance measurement is a destructive technique, as it requires cleav-

ing the substrate and grinding a shallow bevel into the edge. See Fig. 10.41.The

angle of the bevel is chosen so that the depth of the junction to be probed will be

spread over several lateral measurements. A set of very sharp, closely spaced metal

or carbide points is stepped along this beveled surface, and the effective measure-

ment depth is then obtained geometrically as the lateral distance moved multiplied

by the tangent of the bevel angle. Sufﬁcient pressure is applied to the small tips to

actually alter the phase of the silicon material in close proximity to the tip.

Fig. 10.41 Spreading

resistance technique

apparatus. The probe points

are stepped along a bevel

ground in the silicon.

Inﬂections in the carrier

concentration correspond to

n–p junctions

This high-pressure beta-tin structure silicon allotrope is metallic in character

[84], allowing good ohmic contact formation even with relatively light silicon dop-

ing levels. The current at a given bias voltage, usually a few millivolts, is measured

at each point, allowing construction of a plot of spreading resistance versus posi-

tion. The relationship between the measured spreading resistance and the resistivity

of material near each point by is given by

808 A.D. Raisanen

, (10.9)

where a is the radius of the probe tips. The local resistivity number is corrected for

sampling volume effects and the carrier concentration is extracted from empirical

mobility calibration tables. In practice it is difﬁcult to accurately relate the local

resistivity to dopant concentration without the use of calibrated resistivity standards.

It is possible to extract the type of the semiconductor with the same measurement

geometry, except that no voltage bias is applied and one of the tips is heated with

respect to the other.

A small voltage is generated between the probes by the Seebeck effect [85]. The

polarity of this voltage is determined by the semiconductor type, with the hot probe

becoming positive for n-type material and negative for p-type material. Once a car-

rier concentration proﬁle is obtained, it can be related to the actual dopant proﬁle

by iterative solution of Poisson’s equation [86]. Alternatively, some process mod-

eling software such as ATHENA (Silvaco Corp, Santa Clara, CA) has a spreading

resistance simulation option built in, allowing the anticipated spreading resistance

proﬁle to be constructed for comparison with measurements.

An in-house spreading resistance proﬁling capability is often beyond the reach

of many laboratories, but fortunately commercial vendors such as Solecon Labs in

Reno, NV are available to provide this service for a nominal cost. Some workers

include process monitor wafers in each implant and diffusion process to facilitate

spreading resistance analysis of junctions, but it is also straightforward to include

test “strips” for each doping process on device wafers that are large enough to cut

and bevel, typically at least 50 × 500 μm or larger.

Test structures fabricated on semiconductor device wafers are another convenient

method of verifying dopant parameters or analyzing process anomalies. Properly

designed, Van der Pauw and Kelvin resistor structures illustrated in Fig. 10.42 can

be used to measure sheet resistances, lateral diffusion, and other parameters on com-

pleted or in-process wafers [7, 59]. These structures utilize four-point measurement

geometries and are well suited for modestly equipped laboratories, as meaningful

measurements can be made with simple power supplies, voltmeters, and ammeters.

Resistivity of a layer measured by a symmetrical Van der Pauw structure [87], as

illustrated in Fig. 10.42a, is expressed as

ln 2

R. (10.10)

where

R =





(10.11)

in units of ohms/square.

In practice, one simply applies a current ﬂow across two neighboring termi-

nals, and measures a voltage drop across the other two terminals. All terminals are

rotated one position and the measurement is repeated, until all four combinations

10 Doping Processes for MEMS 809

have been measured. These resistance measurements are averaged and the geomet-

ric correction factor is applied to extract the sheet resistance R

. Nonsymmetrical

structures are possible to measure, but are not straightforward to measure analyti-

cally. Symmetrical structures as illustrated are relatively simple mathematically to

analyze. A related structure, the Kelvin resistor, is illustrated in Fig. 10.42b.This

structure consists of two legs of material on two different layers, such as on a polysil-

icon layer and a metal layer, with a contact at the intersection. A current is applied

across two dissimilar terminals as shown, and the voltage drop is measured across

the other two dissimilar terminals. The contact resistance between the two materials

is then simply V/I.

10.8.2 Junction Staining Techniques

Determination of junction depths can be performed by chemically decorating the

n- and p-type semiconductor regions by means of a stain and directly observing

the decorated regions with a microscope. A remarkably large variety of stains has

been reported by various workers for speciﬁc applications [30, 88, 89], but the most

common stain chemistries for silicon contain dilute hydroﬂuoric acid and/or nitric

acid. A number of commercially prepared stain solutions are also available for dif-

ferent materials that avoid the use of hydroﬂuoric acid for safety reasons, such as

the Safe-T-Stain line of materials from Epak Electronics in Somerset, UK.

Effectiveness of the stain typically depends on the level of doping of the semi-

conductor, and is often enhanced by applying bright illumination during the staining

process (providing hole injection which drives many of these silicon oxidation reac-

tions). The mechanism of the stain is closely related to the production of porous

silicon and the electrochemical etch stop techniques described in previous sections,

with partial oxides of silicon produced at the surface of the doped regions, providing

visual contrast by interference of light in the thin oxide.

The edge of the sample to be examined is beveled at a shallow angle as in the

spreading resistance technique, to magnify the depth of the junction laterally as

the cosine of the bevel angle. As beveled edges are somewhat difﬁcult to produce

quickly and reproducibly, commercial apparatus for providing a v-shaped groove for

Fig. 10.42 (a)VanderPauw

structure for measuring sheet

resistance of a layer, and (b)

Kelvin structure for

measuring contact resistance

between two layers

810 A.D. Raisanen

junction staining studies is commonplace, as are systems for producing a shallow

hemispherical crater in the surface of a sample with a spherical ball-bearing lap.

10.8.3 SIMS

Secondary ion mass spectroscopy (SIMS) is a powerful technique for measuring the

composition of surfaces and near-surface regions [90]. See Fig. 10.43. This method

focuses a beam of ions on a surface, typically argon but often xenon, oxygen, or

cesium, to sputter material from the surface.

Fig. 10.43 Schematic of a

secondary ion mass

spectroscopy measurement.

As the ion beam etches

through each layer, the

composition of the layer can

be determined and a complete

depth proﬁle of the surface is

obtained

The sputtered surface atoms are collected by a mass spectrometer and analyzed

to produce an elemental ﬁngerprint of the surface. At sufﬁciently high ion currents, a

crater is eroded in the surface allowing the chemical composition of the substrate to

be measured as a function of depth below the surface. The concentration of dopants

as a function of depth is easily plotted, with sensitivities to atomic concentrations as

low as 10

atoms/cm

in some instances. Precise calibration of the depth scale can

be problematic, as sputter yield depends signiﬁcantly on the matrix of the material

being sputtered [90]. Various thin-ﬁlm standards are generally used to provide a

calibration of sputter etch rate. High sputter etch rates also produce some degree of

intermixing at the surface being analyzed, limiting depth resolution somewhat.

10.8.4 Case Study: Characterizing Junctions and Diagnosing

Implant Anomalies

Determining the fraction of dopant that has been electrically activated is a common

task when a very low thermal budget process is designed. If the drive-in temperature

is too low, or the drive-in time is too short, only partial activation will occur, and

device properties will be adversely affected by having a low carrier concentration.

10 Doping Processes for MEMS 811

In this example, structures on a silicon on glass (SOG) wafer would be seriously

damaged by any thermal processing in excess of 600

◦

C, and would exhibit degra-

dation with time even at this relatively low temperature. The process ﬂow requires

a shallow phosphorus implant to provide heavily doped regions for source/drain

regions of transistors and for contacts. The desired phosphorus implant dose of

1 × 10

atoms/cm

was expected to be difﬁcult to fully activate as it would cause

severe crystalline damage without fully amorphizing the silicon surface region,

making solid epitaxy processes at the low 600

◦

C anneal temperature relatively inef-

fective at restoring crystalline order. A minimum total annealing time was desired

to minimize damage to our wafers, and to minimize diffusion distance to keep the

junction shallow.

Two measurements of completed junctions were performed to verify that the

annealing time was sufﬁcient. First, spreading resistance measurements were per-

formed to extract the carrier concentration depth proﬁle. A SIMS analysis was also

performed on pieces of the same wafer to measure the total dopant depth proﬁle.

These two measurements are plotted in Fig. 10.44.

The SIMS proﬁle illustrates the distribution of phosphorus atoms in the SOI layer

regardless of whether they have been incorporated in the silicon crystal structure, or

are simply occupying interstitial or damage sites. The spreading resistance proﬁle

shows only the concentration of electrical carriers, not the atoms themselves. The

Fig. 10.44 Comparison of SIMS and SRP measurements of a phosphorus implant annealed at low

temperature. A substantial amount of inactive dopant is present at the surface. Data courtesy of

Professor Karl Hirschman at Rochester Institute of Technology

812 A.D. Raisanen

two analytical methods are highly complementary, probing the dopant concentra-

tion with different physical methods to provide a proﬁle of inactive dopants as well

as the usual carrier concentration proﬁle. We see that the surface region contains

a large fraction of phosphorus that does not add to the carrier concentration i nven-

tory. In fact, the fraction of dopant activated near the surface is only on the order of

25% of the total. Deeper in the SOI layer, the dopant is nearly completely active, so

the total activation fraction throughout the implanted region is closer to 33%. This

degree of activation proved to be sufﬁcient for the source/drain regions of the transis-

tors. Complete activation of this implant will require a longer or higher temperature

anneal.

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