774 A.D. Raisanen
Thermal budget Activation of doped regions will generally require anneal or diffusion
temperatures >900
◦
C. Te mperature-sensitive components can be fabricated
on the wafer once the dopants have been activated, but will need to be
protected from t he etch solution by passivation layers or fixturing.
Selectivity Selectivity between n and p silicon-doped regions is reported at 200:1 in KOH
[43] and as high as 3000:1 in EDP [31].
Viable etchants KOH, EDP, and TMAH all exhibit this effect.
Material
compatibility
Same general materials requirements as the underlying KOH, EDP, and TMAH
etch solution. Good electrical contacts must be made to the n-doped layer,
and these contacts must be protected from the etchant.
10.3 In Situ Doping
One of the most effective methods of doping a semiconductor material is during the
growth of that material. Incorporation of dopant atoms during the high-temperature
growth phase results in an undamaged crystal structure with activated dopants,
avoiding the need for subsequent annealing processes and large thermal budgets.
Unfortunately, only bulk material or blanket films can be easily formed in this man-
ner, so complex device structures will generally require some additional processing
technique.
10.3.1 Chemical Vapor Deposition
Polysilicon is a polycrystalline form of silicon commonly used as a thin-film
mechanical material in MEMS and as an electronic gate for MOS electronic devices.
Polysilicon is straightforward to deposit on a wafer surface with chemical vapor
deposition techniques, and is easily etched with a variety of wet chemical and dry
plasma processes. It is compatible with high temperatures, thermally matched to the
underlying silicon wafer, and can be doped to achieve a wide range of conductivity
values.
As stated above, polysilicon is typically deposited using a chemical vapor depo-
sition process in a low-pressure three-zone tube furnace, although the process is also
compatible with single-wafer deposition equipment such as used in cluster tools. A
common arrangement is illustrated in Fig. 10.16. Wafers stored vertically in a car-
rier are centered in a three-zone quartz hot wall furnace that is evacuated with a
vacuum pump. A throttle valve controlled by a pressure sensor is normally placed
at the output port to allow continuous closed loop control of the process pressure.
Reactants are introduced at the front of the tube. Silane (SiH
4
) is the most com-
mon reactant gas, but dichlorosilane (SiH
2
Cl
2
) and silicon tetrachloride (SiCl
4
)are
occasionally used as well. At the wafer surface, silane is broken down to produce
elemental silicon and hydrogen gas.
Minor process details, such as reactor vacuum integrity, carbon and oxygen
contamination, and wafer fixturing details can produce significant variations in