Ghodssi R., Lin P., MEMS Materials and Processes Handbook

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624 D.W. Burns

from the front or more commonly the back of a wafer can enhance and even mod-

ulate the pore diameter [507]. An etch bath that accommodates one or more wafers

and a working or counterelectrode along with an external power supply or poten-

tiostat allows the electrochemical etching of silicon, and under select conditions,

porous silicon, as illustrated in Fig. 8.18. External light illumination (not shown)

may be applied through one of the walls of the etch tank and into a ﬁxture that holds

the wafer. Alternatively, a side or bottom of the etch tank may be modiﬁed to secure

the wafer in a leak-tight manner and allow light to be applied externally while the

etchant acts on the inner surface.

Etch

Bath

Etchant

Patterned

Wafer

(Anode)

Ohmic

Contact

Voltage Supply

Counter

Electrode

Protective

Mask

V+

Porous

Silicon

(+)

(–)

Fig. 8.18 Porous silicon

formation is dependent

primarily on dopant type, HF

concentration, applied

voltage, current density, and

illumination levels. The

silicon wafer can be masked

to form porous silicon or

completely remove the silicon

at selective locations.

Selective doping and biasing

of the substrate can produce

controlled 3-D structures

At large anodic (positive) bias, the p-type and n-type material are electro-

chemically etched and disappear. At lower anodic bias, p-type material can be

selectively etched over the n-type. Combinations of n-and p-type diffusions, epi

layers with various bias levels, and control of incident light can result in selec-

tive etching or selective porous silicon formation with subsequent removal to form

three-dimensional microstructures. Masking with metal masks such as gold with

an adhesion layer, unbiased polysilicon layers, silicon carbide, and silicon nitride

allow localized etching or porous silicon formation. Silicon dioxide and even pho-

toresist may be used for short times in a dilute HF solution. Many excellent reviews

and summaries of porous silicon formation that emphasize micromachining aspects

are available to the interested reader [557, 559, 591–595]. Materials such as GaAs

and other III-V compounds also exhibit porous structures with wet electrochemical

etching [596].

8.8.1 Nanoporous, Mesoporous, and Macroporous Silicon

Formation

P-type silicon can be made porous with anodic biasing at nearly every doping level.

N-type silicon requires relatively heavy doping in excess of about 1 × 10

−3

with anodic biasing, and exhibits a diminished formation rate between 1 ×10

and

1 ×10

−3

[556]. Visible light may be applied to transform n-type material into

8 MEMS Wet-Etch Processes and Procedures 625

porous silicon for low doping levels, which generally has little effect on p-type or

degenerate n-type material.

Macroporous silicon is obtained from low-doped n-type silicon with anodic bias

and light in an HF solution, with pores having geometries larger than ∼500 Å that

generally grow perpendicular to the surface that can be initiated with prepatterned

surface pits [595]. Micron-diameter pore sizes are controlled in part by the doping,

the HF concentration and the applied current density [597]. Mesoporous silicon is

formed from heavily doped degenerate n-type or p-type silicon, resulting in large

inner surface areas and pore sizes between 20 and 500 Å with smooth surfaces for

subsequent processing. Nanoporous silicon, also referred to as microporous silicon,

is formed from low-doped p-type or low-doped n-type (with light assistance) silicon,

resulting in geometries less than 20 Å with very high inner surface area and possible

luminescence.

The conditions for porous silicon formation change for p-type and n-type sili-

con when illuminated [559]. Without light and without bias, there are essentially no

reactions at either the p-type or n-type silicon surfaces when exposed to the etchant.

Without light and with low applied anodic bias (positive on the silicon with respect

to a counter- or working electrode), porous silicon forms in the p-type material and

no reactions occur at the n-type surface. For cathodically biased (negative) silicon

and no light, p-type silicon shows no reaction whereas the n-type surface evolves

hydrogen. With light and without bias, the p-type material weakly evolves hydro-

gen and porous silicon is formed in the n-type material. With light and applied

anodic bias, porous silicon forms in t he p-type material and the n-type material. For

cathodically biased silicon with light, hydrogen is evolved at both the p-type and

n-type silicon surfaces. With high applied anodic bias, electrochemical etching (i.e.,

electropolishing) occurs for both p-type and n-type silicon [598, 599]. Organic elec-

trolytes may also be effective in the formation of porous silicon [592]. Some porous

silicon etch rates and etchant details are provided in Table 8.35.

8.8.2 Selective Porous Silicon Removal

As porous silicon can have pore sizes less than 20 Å and more than 500 Å (up to

10 µm for macroporous silicon) with porosities of 50% or higher, large amounts of

surface area occur that enable etching or oxidizing at effective rates much higher

than the bulk, allowing for the selective removal of the porous silicon even with

nonselective etchants. A list of some approaches to the selective removal of porous

silicon is found in Table 8.36

8.8.3 Examples: Porous Silicon Formation

8.8.3.1 Example 1: Chemical Porous Silicon Formation

A 1–3  cm p-type boron doped wafer is inserted into a polypropylene beaker with a

mixture of HF(49%):HNO

(70%):H

O 4:1:5 that is primed with several fragments

of a silicon wafer prior to adding the DI water. The wafer is s tain-etched between

626 D.W. Burns

Table 8.35 Porous silicon formation rates and processes

Material

Formation

rate

(Å/s) Etchant Remarks and references

1 Silicon (Si), n-type

(100)

HF(49%):H

1:9

◦

C; DHF etchant (9:1); 5 wt% HF; n-type (2-6  cm) silicon with

implanted backside transparent contact; +2 V applied to silicon

anode; light intensity modulation; pre-structured with oxide mask

and shallow TMAH etch pits; macroporous silicon [507, 508]

2 Silicon (Si), p-type

(100)

30 HF(49%):H

2:3

Room temperature; DHF etchant (3:2); 20 wt% HF; p-layer with

1 × 10

−3

boron between two n-layers with 1 × 10

−3

dopant; lateral formation rate; no external bias; 100 mW/cm

light

intensity from topside; porous silicon [503]

3 Silicon (Si),

–

(substrate), (100)

HF(49%):H

2:3

Room temperature; DHF etchant (3:2); 20 wt% HF; p

porous layers

∼ 1 × 10

−3

each, n

–

barrier layers ∼ 5 × 10

−2

p-substrate ∼2 × 10

–2

(8–16  cm); multi-level porous

silicon formation; two masking steps [600]

4 Silicon (Si) 65 HF(49%)

undiluted

Room temperature; HF etchant (49 wt%); 5 mA/cm

(65 Å/s) then

100 mA/cm

for dual-rate anodization; subsequent epi deposition,

local patterning and etching of epi, then rapid (>100x) wet

oxidation of porous silicon layers at 950

◦

C; silicon-on-oxidized

porous silicon (SOPS) process for isolated silicon islands [601]

5 Silicon (Si), n-type

(100)

625 HF(49%):Ethanol

1:2

Room temperature; 1.4–2.3  cm; anodic bias; 25 mA/cm

;ﬁne

pores; augmented with thin gold upper electrode; emits visible light

[602]

6 Silicon (Si), p-type

(100)

500 HF(49%):Ethanol

1:1

Room temperature; Hf etchant (25%) with ethanol; p-type (1  cm)

substrate with implanted backside contact; anodic biasing;

230 mA/cm

(formation rate reduces to 50 Å/s for 20 mA/cm

);

mask with oxide, n-doped poly-Si, NiCr/Au and PR; a lcohol added

to improve bubble release [558]

7 Silicon (Si), p

–

type

(100)

4000 HF(49%):Ethanol

1:1

Elevated temperature; boron-doped 1.0  cm substrate;

1000 mA/cm

; dark; microporous silicon [603]

8 MEMS Wet-Etch Processes and Procedures 627

Table 8.35 (continued)

Material

Formation

rate (Å/s) Etchant Remarks and references

8 Silicon (Si), n

type

(100)

7500 HF(49%):Ethanol

1:1

Elevated temperature; n-doped 0.067  cm substrate; 400 mA/cm

;

dark; mesoporous silicon [603]

9 Silicon (Si), n

–

type

(100)

15000 HF(49%):Ethanol

1:1

Elevated temperature; phosphorus-doped 5.0  cm substrate;

1000 mA/cm

; backside illumination; macroporous silicon;

pre-structured surface [603]

10 Silicon (Si), p

type

(100)

HF(49%):Ethanol

2:1

Room temperature; boron-doped 0.01–0.02  cm substrate;

7mA/cm

;12µm-thick porous silicon with 15% porosity;

subsequent low-temperature thin oxidation, brief HF dip, epi

deposition, 1000 Å oxidation and bonded to oxidized Si handle

wafer, then handle wafer is ground to expose porous silicon which

is then stripped in HF:H

1:5; ELTRAN process [590]

11 Silicon (Si), p-type,

(100)

HF(49%):

HNO

(70%):H

1:5:10

Room temperature (no intentional heating); HNW etchant; 0.05  cm;

stain etching; no bias; no impact by room light while etching;

generates visible stains; visibly luminescent with applied UV light;

prime solution with silicon fragments prior to adding water; 30-s to

10-min etches [604]

12 Silicon (Si), p-type,

(111)

HF(49%):

HNO

(70%):H

1:5:10

Room temperature; HNW etchant; 30–40  cm; stain etching; no bias;

luminescent with UV light [605]

13 Silicon (Si), p-type,

(100)

HF(49%):

HNO

(70%):H

4:1:5

Room temperature (no intentional heating); HNW etchant; 1–3  cm;

stain etching; no bias; generates visible stains; visibly luminescent

with applied UV light; also (111) material and n-type material [604]

14 Silicon (Si), p

–

type,

(100)

450 HF(49%):H

4:1

Room temperature; DHF etchant (1:4); 40 wt% HF; FIPOS process;

1.5  cm; proton-implanted silicon n-type islands; 50 mA/cm

;

dual chamber for anodization; oxidize porous silicon (10–20x faster

than thermal) and restore islands to p-type [606]

628 D.W. Burns

Table 8.36 Selective porous silicon removal rates and processes

Material

Etch rate

(Å/s) Etchant Remarks and references

1 Silicon

(Si),

porous

400 HF(49%):

(30%)

1:5

Room temperature; p

porous silicon

with 15% porosity; doesn’t

signiﬁcantly etch Si (<0.01 Å/s)

[590]

2 Silicon

(Si),

porous

HF(49%):

HNO

(70%):

Acetic 3:16:1

Room temperature; HNA etchant; 5-s

dip may be adequate [509]

3 Silicon

(Si),

porous

KOH:H

10 g:1000 mL

Room temperature; KOH etchant

(1 wt%); 0.1 wt% KOH for

nanoporous silicon to 10 wt% KOH

for mesoporous silicon; also TMAH

etchant or TMAH-based developer

[557, 559, 595]

4 Silicon

(Si),

porous

KOH:H

250 g:750 mL

◦

C; KOH etchant (25 wt%); 30-s

dip may be adequate [509]

5 Silicon

(Si),

porous

Oxidize then HF Room temperature; HF, B HF, or DHF

etchant; oxidize at 1000

◦

C(wet)

then etch [503]

30 s and 10 min to produce a porous silicon layer about 0.5 µm thick. After rinsing

and drying, the resulting stains are visually luminescent with a reddish-orange color

when exposed to UV light at 365 nm. Exposure to light during stain-etching does

not affect the result [604].

8.8.3.2 Example 2: Nanoporous Silicon Formation

A 525 µm-thick p-type double-side polished silicon wafer with a resistivity of 1–

10  cm is implanted with boron to a dosage of 1 × 10

−2

, annealed and then

coated with a 0.5 µm-thick layer of aluminum layer on one side. The wafer is placed

in a ﬁxture that allows electrical contact to the aluminum layer via a metal spring

while keeping the metalicized side dry. The ﬁxture is inserted into a 1:1 mixture

of HF(49%) and ethanol with the metal spring connected to an adjustable voltage

supply. A platinum mesh serving as a counterelectrode is placed in the etchant and

also connected to the power supply. The etch tank is covered to keep the wafer dark.

The voltage is adjusted to supply 10 mA/cm

. After 20 min, nanoporous silicon has

formed to a depth of 10 µm. The wafer is rinsed in DI water, dried, and removed

from the ﬁxture [603].

8.8.3.3 Example 3: Mesoporous Silicon Formation

A lightly doped n-type wafer with a 10 µm-thick phosphorus-doped epi layer having

a resistivity of 0.07  cm and an ohmic backside contact is inserted into a ﬁxture

8 MEMS Wet-Etch Processes and Procedures 629

and placed in a 1:1 mixture of HF(49%):ethanol at room temperature. A power

supply provides 15 mA/cm

of electrical current between the wafer and a platinum

electrode in the etchant for 5 min to form a mesoporous silicon layer that is 10 µm

thick and stops on the lightly doped substrate [603].

8.8.3.4 Example 4: Macroporous Silicon Formation

An n-type (100) silicon wafer with a resistivity of 2–6  cm and a single 150 µm-

thick s ilicon diaphragm has a patterned frontside oxide and a cleared backside that

is implanted to form an n

contact. While in a ﬁxture, the frontside is etched in

TMAH(25 wt%) etchant for 3

min at 80

◦

C to form pyramidal pits that are 2 µm

wide on each side and periodically spaced in the x- and y-directions with a center-

to-center spacing of 4 µm. The wafer is placed in a second ﬁxture. The ﬁxture and a

platinum counterelectrode are inserted into an etch bath with HF(5 wt%) and some

surfactant at 15

◦

C, and the wafer is biased at +2 V. Light from an external halogen

lamp illuminates the wafer backside, and the n-silicon is anodically etched from the

frontside starting at the bottoms of the pyramidal pits. As the pores are formed, the

light is modulated to vary the diameter of the pore holes with a 4 µm period until

a depth of about 130 µm is reached. After opening the pores from the backside by

removing the remaining silicon, the membranes are immersed in TMAH(25 wt%)

for 60 min at 5

◦

C to encourage (110) etching over (100) etching throughout the

length of the pores, resulting in the periodic interconnecting of adjacent pores in a

3-D structure with bandgap properties as a photonic crystal [507].

8.9 Layer Delineation and Defect Determination

with Wet Etchants

Wet chemical etching can be used to delineate thin ﬁlms and substrate layers for vali-

dating designs and processes, and to detect and locate defects that cause yield losses

or long-term reliability concerns. These etchants are often applied to devices that

have been cross-sectioned to allow direct observation of structure details. Absolute

doping levels may be intractable, however, dopant-selective etchants can reveal the

type and relative doping levels in a substrate and delineate p–n junctions by decorat-

ing and making visible variations and transitions in the doped regions for veriﬁcation

of implant and epi proﬁles, thermal diffusion coefﬁcients, and the thickness of

various layers.

Although difﬁcult to locate and observe on a molecular scale, crystalline defects

such as dislocations and stacking faults can be detected with selective etchants.

Short and sometimes extended etch times are required to generate sizeable etch

pits in a substrate that indicates the presence of one or a series of defects, beneﬁting

from the property of some etchants to attack defects preferentially. Etchants may be

preferential to dislocations and defects that surround individual crystalline grains,

630 D.W. Burns

and grain boundaries in deposited ﬁlms such as polysilicon and aluminum can be

selectively etched to reveal the grain size.

Cross-sectioning of devices for process characterization, veriﬁcation, qualiﬁ-

cation, or failure analysis may involve the delineation of layers to enhance their

visibility in microscope or SEM micrographs. The micrographs can be enhanced

by selective decoration or the generation of preferentially etched steps in a cross-

sectioned stack of materials. Selective etchants for delineating different oxides,

dielectrics, metals, and semiconducting regions in a device are described below.

Other etchants are suitable for locating and determining the density of defects such

as pinholes in deposited layers. This section ends with several examples of junction

location and layer delineation. Many of the etchants and techniques presented in this

section require special care and expertise to use well, as many are light-sensitive or

can etch portions of the sample very rapidly. Several excellent references can be

consulted for further details and discussions [607–610].

8.9.1 Dopant Level and Defect Determination with Wet Etchants

Selective etchants, such as hi–low etchants or p–n junction delineation etchants,

can be used to determine junction depths for single p–n junctions or for complex

conﬁgurations such as twin-well BiCMOS processes with n-type and p-type buried

layers and multiple levels of interconnect. These etchants may stain or discolor one

dopant type over another, or etch one type faster than the other to allow the user to

locate metallurgical junctions in cross-sectioned samples. The hi–low etchants will

etch highly doped material preferentially over lightly doped material. For increased

accuracy in junction depth measurements, lapping and polishing a sample with an

angled mounting ﬁxture as low as 1

◦

may be used. SEM micrographs often use

◦

mounts for accurate dimensioning between layers. A series of dopant-sensitive

etchants including hi–low etchants, p–n junction etchants and staining etchants for

silicon are listed in Table 8.37.

Defects in crystalline or polycrystalline samples may be determined by the for-

mation of etch pits or other visible features with orientation-sensitive etchants that

etch more rapidly in the presence of dislocations and stacking faults in the substrate.

Some of the etchants are more suitable for quantifying defect densities in boules or

wafers of silicon, as they can etch the material quite rapidly. Table 8.38 shows a

series of etchants for decorating defects in silicon with emphasis placed on etchants

containing common cleanroom chemicals. Table 8.39 presents additional etchants

containing metal compounds for decorating defects in silicon that may be more suit-

able for a failure analysis laboratory. Table 8.40 includes etchants that preferentially

etch grain boundaries in certain materials of interest. Compilations of dislocation

etchants for other materials such as III-V and II-VI compounds can be found in

several references [76, 611, 612].

8 MEMS Wet-Etch Processes and Procedures 631

Table 8.37 Silicon dopant-sensitive etchants and etch processes

Material

Etch rate

(Å/s) Etchant Remarks and references

1 Silicon (Si), n

Silicon (Si), n

Silicon (Si), p

0.8–400 HF(49%):

HNO

(70%):Acetic

1:3:10

◦

C; HNA etchant; also Dash etchant; hi–low etchant; bevel and polish sample; strong

illumination; swab, squirt or drip etchant; 1–15 s; look for discoloration; etches lightly

doped Si(100) 22 Å/s, Si(111) 0.8 Å/s; etches heavily doped n-type or p-type Si faster

(∼400 Å/s f or < 5 × 10

−3

); 10–15 s for cross-sectioning; stain will appear and

steps may be generated [45, 76, 441, 613–615]

2 Silicon (Si), n

Silicon (Si), n

Silicon (Si), p

HF(49%):

HNO

(70%)

50 mL: 6 drops

Room temperature; hi–low etchant; bevel and polish sample; strong illumination; swab,

squirt or drip etchant; 1–15 s; look for discoloration on p-type side [613, 616, 617]

3 Silicon (Si),

/p, alloyed

with Al

Silicon (Si),

/n, alloyed

with Al

HF(49%):

HNO

(70%):Acetic

1:3:6

Room temperature; HNA etchant; p–n junction etchant; bevel and polish sample ∼3

◦

;no

illumination; swab, squirt, or drip etchant; 10–60 s; generates step [613]

4 Silicon (Si), n/p

Silicon (Si), p/n

HF(49%)

undiluted

Room temperature; HF etchant (49 wt%); p–n junction etchant; strong illumination;

n-type turns dark [618]

5 Silicon (Si), n/p

Silicon (Si), p/n

HF(49%):

HNO

(70%)

200:1

Room temperature; p–n junction e tchant; 5–10 s; illumination ampliﬁes effect; p-type is

stained [45]

632 D.W. Burns

Table 8.37 (continued)

Material

Etch rate

(Å/s) Etchant Remarks and references

6 Silicon (Si), n/p

Silicon (Si), p/n

HF(49%):

HNO

(70%)

3:97

Room temperature; p–n junction e tchant; also 97:3 etchant; 3–5 s; n-type is stained [45]

7 Silicon (Si), n/p

Silicon (Si), p/n

HF(49%):

CuSO

O:H

10 mL:8 g:980 mL

Room temperature; p–n junction e tchant; copper sulphate etchant; stains dopant levels

down to 1 ×10

−3

; bevel lap and polish prior; 5–60 s with illumination; rinse and

dry; n-type is stained [45, 619]

8 Silicon (Si), n/p

Silicon (Si), p/n

HF(49%):H

:KI:

2 mL:5 g:5 mg: 50

Room temperature; Sponheimer–Mills etchant; p–n junction etchant; add KI last; bevel

lap and polish; add one part acetone to 30 parts staining solution before use; ∼25 s in

ultrasonic; simultaneous delineation of active devices including junctions, implants,

oxides, nitrides, aluminum, tungsten, and polysilicon; p-type preferentially etched [45,

620]

8 MEMS Wet-Etch Processes and Procedures 633

Table 8.38 Silicon dislocation delineation etchants and etch processes: I

Material

Etch rate

(Å/s) Etchant Remarks and references

1 Silicon (Si) 830 HF(49%):HNO

(70%):Acetic

8:75:17

◦

C; HNA etchant; planar etchant; all planes [441]

2 Silicon (Si) HF(49%):

HNO

(70%):Acetic

2:3:2

Room temperature; HNA etchant; silicon polishing etchant; 2–3 min

[45]

3 Silicon (Si),

(100), (110),

(111)

22 HF(49%):

HNO

(70%):Acetic

1:3:10

Room temperature; HNA etchant; also Dash etchant; reveals

dislocations and stacking faults; 15–20 min for (100) and (110)

surfaces; ∼4 h for (111) surfaces; etch rate for n

–

or p

–

(100)

material; faster for n

and p

(∼400 Å/s) [441, 611, 614, 615]

4 Silicon (Si) HF(49%):

HNO

(70%):Acetic

3:5:3

Room temperature; HNA etchant; also CP-4A etchant; highlights

twinning defects in silicon [609]

5 Silicon (Si), poly HF(49%):

HNO

(70%):Acetic

1:3:6

Room temperature; HNA etchant; delineates polysilicon grain

boundaries; ∼6min[609]

6 Silicon (Si), poly 1000 HF(49%):

HNO

(70%):Acetic

36:1:20

Room temperature; HNA etchant; also Sopori etchant; defect etchant

for polysilicon; dislocations and stacking faults; 5–30 s; cool to

◦

C for slower etch rates; HNO

component may be doubled [621]