Ghodssi R., Lin P., MEMS Materials and Processes Handbook

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614 D.W. Burns

Table 8.32 (continued)

Structural

layer/sacriﬁcial layer

Etch rate

(Å/s) Etchant Remarks and references

10 Nickel (Ni)/chromium

(Cr)

350 HCl(38%):H

1:1

Room temperature; electroplated Ni with Cu seed layer; doesn’t

signiﬁcantly etch Cu or Ni [538]

11 Nickel (Ni)/oxide

(SiO

-PSG)

3300 HF(49%)

undiluted

Room temperature; HF etchant (49 wt%); 1000

◦

C PSG anneal; hexsil

process; electroless nickel sandwiched within doped and undoped

polysilicon; Triton X-100 surfactant added to etchant [539]

12 Nickel (Ni)/oxide

(SiO

)

BHF Room temperature; BHF etchant; electroplated nickel through LIGA

PMMA mold; strip Ni seed layer in dilute nitric acid prior; single

mask [439]

13 Nickel (Ni)/photoresist

(PR)

Acetone Room temperature; electroplated nickel; sacriﬁcial copper plating

base; thin photoresist sacriﬁcial layer; thick photoresist plating

mold [540]

14 Nickel (Ni)/Ti HCl(38%):H

1:6

Room temperature etchant, followed by very dilute HF etch for

removal of titanium sacriﬁcial layer; electroplated nickel through

PMMA mold; sacriﬁcial LIGA (SLIGA); remove underlying

polyimide (PI) with ammonium hydroxide [541–544]

15 Nickel (Ni)/zinc (Zn) 28 NH

OH(29%):

(30%):NaOH:

10 mL:10 mL:3 g:

100 mL

60–70

◦

C etch temperature; sacriﬁcial LIGA (SLIGA); sputtered Ti/Cu

seed layer; follow with NH

OH(29%):H

(30%):H

O 100

mL:100 mL:500 mL [545]

16 Nickel–iron

(NiFe)/copper (Cu)

◦

C NiFe plating temperature; copper or photoresist sacriﬁcial layer

[536]

17 Nickel–iron (NiFe, iron-

poor)/nickel–iron

(NiFe, iron-rich)

1.4–220 Acetic:H

1:9

◦

C acetic acid etch; pulsed electrolyte agitation for in situ

compositional control; preferentially etches iron-rich layers; low

etch rates without biasing; high etch rates with anodic bias [546]

18 Oxide (SiO

)/silicon

(Si), (100)

EDP 120

◦

C etch; thermal oxide cantilevers with Cr/Au metallization and

buried p

etch stop [547]

8 MEMS Wet-Etch Processes and Procedures 615

Table 8.32 (continued)

Structural

layer/sacriﬁcial layer

Etch rate

(Å/s) Etchant Remarks and references

19 Oxide (SiO

)/silicon

(Si), (100)

∼12 TMAH(25 wt%):

silicic acid:H

80 mL:16 g:150 mL

Deposited and thermal oxides with embedded aluminum and

polysilicon features from CMOS process; 70

◦

C etch for 24 h; also

etched in XeF

[514]

20 Oxide

(SiO

)/polysilicon

(Si, poly)

1900 XeF

(vapor)

3Torr

Room temperature; XeF

vapor etchant; 1000:1 selectivity over

PECVD and thermal SiO

; doesn’t signiﬁcantly etch SiC [519]

21 Parylene C/photoresist

(PR)

550 Acetone

undiluted

Room temperature; parylene C micro-channels; novolak-diazoquinone

positive PR; etches ∼1 mm in 30 min; results are linear with the

square root of time; slows moderately for postbaked resist [548]

22 Polyimide

(PI)/aluminum (Al)

350 H

(85%):

HNO

(70%):Acetic:

Room temperature; PAN etchant; 400

◦

C cure for spin-coated

polyimide; evaporated Al sacriﬁcial layer [549, 550]

23 Polyimide (PI)/oxide

(SiO

, PSG)

BHF Room temperature; BHF etchant; 140

◦

C cure for spin-coated

polyimide; PSG sacriﬁcial layer; polyimide hinges for polysilicon

structural layers; patterned apertures in poly for faster etching [551]

24 Polyimide

(PI)/photoresist (PR)

Heat 450

◦

C; thermal decomposition (dry release) of negative-acting

polynorbornene (Avatrel 2000P); also SiO

-PECVD structural layer

[552]

25 Silicon (a-SI, amor-

phous)/aluminum

(Al)

(85%):

HNO

(70%):Acetic:

8:1:1:5

Room temperature; PAN etchant; 415

◦

C amorphous silicon anneal;

PAN etchant at 55

◦

C; evaporated aluminum sacriﬁcial layer [553]

26 Silicon (Si)/silicon (Si) HF(49%):

HNO

(70%):

Acetic

1:3:8

Room temperature; HNA etchant; 335–660

◦

C bond to 7740 glass;

dissolved wafer process; high (1:3:8) or low (EDP) doped substrate

removal; leave low-doped (1:3:8) or highly doped (EDP) features

on glass [554, 555]

616 D.W. Burns

Table 8.32 (continued)

Structural

layer/sacriﬁcial layer

Etch rate

(Å/s) Etchant Remarks and references

27 Silicon (Si)/silicon (Si),

porous

KOH:H

10 g:1000 mL

Room temperature; KOH etchant (1 wt%); mask with Au, NiCr,

poly-Si (restrictions), PR (limited), Si

,SiO

(limited), SiC; also

polysilicon or nitride-encapsulated structures [556–559]

28 Silicon carbide

(SiC)/polyimide (PI)

670 O

plasma Dry etch; 400

◦

C for PECVD SiC deposition; also SiO

and Al

structural layers on polyimide sacriﬁcial layer [408]

29 Silicon–germanium

(SiGe,

poly)/germanium

(Ge, poly)

50–85 H

(30%)

undiluted

◦

C; etch rate varies with doping level; doesn’t signiﬁcantly etch Si

or Si

1–x

with x >0.4 [560]

30 Silicon nitride

(Si

)/aluminum

(Al)

∼35 H

(85%):

HNO

(70%):Acetic:

16:1:1:2

◦

C; PAN etchant; PECVD silicon nitride; evaporated aluminum

sacriﬁcial layer; through KOH-etched backside cavities [561]

31 Silicon nitride

(Si

)/silicon (Si,

porous)

KOH:H

10 g:1000 mL

Room temperature; KOH etchant (1 wt%); auxiliary sacriﬁcial layer to

expose oxide sacriﬁcial layer from wafer backside [562]

32 SU-8 (PR)/oxide (SiO2,

SOG)

HF(49%):H

1:1

Room temperature; DI water rinse [563]

33 SU-8 (PR)/SU-8 (PR) 330 PGMEA Room temperature; 110

◦

C postbake of SU-8; unexposed lower SU-8

layer dissolves away; Mg mask layer between SU-8 layers; pattern

Mg with HCl; doesn’t signiﬁcantly etch Cr/Au; also SOG or

SiO

(PECVD) as sacriﬁcial layers [564]

34 Titanium (Ti)/gold (Au) Ammonium iodide,

iodine, and

alcohol

Room temperature; deposited titanium; deposited gold sacriﬁcial layer

[565]

35 Tungsten (W)/oxide

(SiO

,LTO)

HF(49%):

F(40%) 1:6

Room temperature; 580

◦

C selective CVD tungsten deposition;

SiO

(LTO) sacriﬁcial layer [566, 567]

8 MEMS Wet-Etch Processes and Procedures 617

8.7.4 Etch Accelerator Layers for Enhanced Sacriﬁcial Layer

Removal

Etch accelerator layers allow an etchant to rapidly etch laterally along a relatively

thin portion of a sacriﬁcial layer, while etching the majority of the sacriﬁcial layer

more slowly yet with an effective etch distance less than the thickness of the sacriﬁ-

cial layer so that the etch time is determined predominantly by the lateral etch rate of

the accelerator layer. Ion-implanted thermal oxides with argon-implanted dosages in

excess of 1 × 10

−2

or phosphorus-doped glass with argon-implanted dosages

in excess of 1 ×10

−2

have been shown to accelerate the lateral etch and cause

an angular sidewall taper to form [568]. Similar effects have been observed for

lateral etching of ion-implanted polysilicon and silicon nitride [569]. As the accel-

erator layer is removed, the etchant is exposed to the bulk of the sacriﬁcial layer

and can remove it relatively quickly, as illustrated in Fig. 8.17. Boron, phospho-

rus, or arsenic-doped glasses etch much faster in HF and buffered HF solutions

for most levels of dopant, dopant type, and HF concentration [570]. Bilaminate

layers of doped and undoped oxides have also been shown to favorably acceler-

ate the lateral etch rate [571]. Other material conﬁgurations such as a polysilicon

layer on top of a single crystal substrate allows an anisotropic etchant to laterally

remove the polysilicon and anisotropically remove portions of the substrate under

the polysilicon regions [572]. Table 8.33 lists some sacriﬁcial etch accelerator layers

and removal recipes.

Etchant

Structural Layer

Sacrificial Layer

Substrate

Etch Accelerator

Layer

Etchant

Structural Layer

Sacrificial Layer

Substrate

Etchant

Structural Layer

Sacrificial Layer

Substrate

Etch Accelerator

Layer

Etchant

Etch Accelerator

Layer

Etchant

Fig. 8.17 Sacriﬁcial etch accelerator layers allow a structure to be undercut rapidly. The sacriﬁcial

layer is structurally altered or augmented with a fast-etching layer so that the lateral etch rate of

the sacriﬁcial layer is effectively enhanced. (a) Lateral etching without an accelerator layer, and

(b) lateral etching with an accelerator layer

618 D.W. Burns

Table 8.33 Sacriﬁcial etch accelerator layers and removal processes

Structural

layer/sacriﬁcial layer

Etch rate

(Å/s) Etchant Remarks and references

1 Oxide (SiO

implanted)/oxide

(SiO

,thermal)

25/17 HF(49%):

F(40%)

1:7

◦

C; BHF etchant (7:1); 3 × 10

−2

Ar implant at 50 keV;

enhancement increases to 4.8 for >1 × 10

−2

Ar at 50 keV or

< 1 × 10

−2

As at 80 keV [568, 569]

2 Oxide (SiO

, PSG,

implanted)/oxide

(SiO

, PSG)

105/65 HF(49%):

F(40%)

1:7

◦

C; BHF etchant (7:1); annealed PSG(7 wt%); 1 × 10

−2

implant at 50 keV [568]

3 Silicon nitride

(Si

implanted)/silicon

nitride (Si

)

5.2:1 H

(85%)

undiluted

160

◦

C; 1 × 10

−2

As implant at 80 keV [569]

4 Silicon (Si, poly,

implanted)/polysilicon

(Si, poly)

2.6:1 HF(49%):

HNO

(70%):H

3:100:4

Room temperature; HNW etchant; 1 × 10

−2

Ar at 50 keV or

1 × 10

−2

As at 80 keV [569]

5 Oxide (SiO

BSG)/oxide

(SiO

, CVD)

12/1.7 HF(49%):

F(40%):H

1:10:100

◦

C; dilute BHF etchant; annealed BSG(30 mol% B

); selectivity

increases with lower BHF concentration and decreases with higher

BHF concentration [570]

6 Oxide

(SiO

-PSG)/oxide

(SiO

, CVD)

43/4 HF(49%):

F(40%):H

1:10:33

◦

C; dilute BHF etchant; annealed PSG(8.2 mol% P

)[570]

7 Oxide (SiO

ASG)/oxide

(SiO

, CVD)

23/13 HF(49%):

F(40%)

1:10

◦

C; BHF etchant (10:1); annealed ASG(4.8 mol% As

)[570]

8 Oxide (SiO

CVD)/oxide

(SiO

,thermal)

90/17 HF(49%):

F(40%)

1:6

◦

C; BHF etchant (6:1); enhancement reduces from 5.3:1 to 3.7:1

with 625

◦

C anneal and 2:1 with 800

◦

C anneal [571]

9 Silicon nitride

(Si

)/polysilicon

(Si, poly) and

Si(100)

KOH:H

540 g:1000 mL

∼850

◦

C silicon nitride deposition; Si(100) sacriﬁcial layer;

polysilicon accelerator layer; KOH etchant (35 wt%)at 80

◦

C[572]

8 MEMS Wet-Etch Processes and Procedures 619

8.7.5 Rinse Liquid Removal and Antistiction Coatings

Undercutting of structural layers by wet-chemical removal of thin-ﬁlm sacriﬁcial

layers presents a special dilemma: how to remove the freestanding structures from

the rinse liquid without causing them to break or stick. Rinsing the etchant and dry-

ing the freestanding microstructures can prove surprisingly difﬁcult, in part because

of the relative magnitude of surface tension and capillary forces that develop

between the structural features and the substrate as the etchant or rinse liquid dries

[573, 574]. Blow-drying and stiction effects during drying can be detrimental to

the process yield. High-stiffness devices such as low- and medium-aspect ratio

beams, plates, and shells provide enough rigidity to overcome capillary forces and

surface-tension effects as the rinse liquid is spun off and the devices are blow-dried.

Low-stiffness devices common in MEMS sensors and actuators may have sidewall

or bottom surfaces that come in contact with other features or the substrate as the

last of the rinse liquid evaporates from around the structures. This temporary contact

may become permanent, causing yield loss.

Devices in operation may be subjected to high forces that cause contact between

surfaces and subsequent sticking. In-use stiction concerns may best be resolved with

appropriate design improvements such as increased structural stiffness or limited

contact area, or with the application of suitable thin coatings around the microstruc-

ture. Release stiction also may be resolved through design by establishing and

adhering to minimum structural stiffness design rules. Reductions in stiction may

be obtained by limiting mechanical contact area during drying or while in use with

structural features such as small detents, protrusions, or dimples in the structural

layer or enhanced surface roughness to limit the exposed surface area in contact

with the substrate, allowing the innate stiffness of the structural layer to restore the

freestanding features after contact is made.

The general rinsing sequence can be augmented for devices with low stiffness

elements: (1) a low surface-tension ﬁnal rinse liquid such as alcohol may be useful

in marginal situations; (2) the exposed surfaces may be chemically altered to reduce

the surface tension effects by roughening or by altering their phobicity; (3) the ﬁnal

rinse liquid may be extracted in a nonliquid state via freezing and sublimation, or

through critical-point drying; (4) the structures may be coated with an effective, low

surface-tension coating prior to drying; or (5) vapor or dry release processes such as

vapor HF or XeF

gas may be adopted for removal of the sacriﬁcial layer that avoid

the use of a liquid altogether.

Freezing and sublimation techniques involve freezing the ﬁnal rinse liquid such

as water, alcohol–water mixtures, or organic compounds such as cyclohexane or

t-butyl alcohol, and then sublimating the frozen material with a vacuum pump or

with enhanced air ﬂow. Full wafers or single die are transferred quickly from the

ﬁnal rinse liquid to decant most of the liquid while preventing air drying, and then

placed on a cooling plate or simply pumped down in a chamber to freeze the thin

layer of liquid remaining on the wafer surfaces. Sublimation of the frozen liquid

begins and fractions of an hour to several hours may be needed to complete the

process.

620 D.W. Burns

Critical point drying can be an effective way to remove rinse liquid after sacri-

ﬁcial etching and avoid microstructure release stiction. At the critical point, liquid

and gas phases coexist at the highest possible temperature. Above this critical tem-

perature, no liquid phase exists. Carbon dioxide with a critical point of 7.38 MPa

at 31.1

◦

C is more suitable than water with a critical point of 22.1 MPa and 374

◦

[575]. Critical point drying with carbon dioxide may be used to r emove ﬁnal rinse

liquid such as isopropyl alcohol or methanol [576, 577]. While under pressure at

room temperature, the rinse liquid is methodically replaced with liquid CO

and

then the chamber is elevated in pressure and temperature above the CO

critical

point. The CO

is then vented while maintaining the temperature above the crit-

ical temperature to allow the devices to be dried without ever crossing a phase

boundary.

Very thin layers of low surface-tension material may be deposited on exposed

surfaces to reduce or prevent release stiction, such as self-assembled monolayers

(SAM). These coatings can also reduce operational stiction, and may be applied

as part of the rinsing sequence or in a later step after the devices have been

dried.

Table 8.34 shows a succession of rinse-liquid removal processes that target

polysilicon microstructures on silicon substrates with or without a buffer or iso-

lation layer. The solvent-intensive processes may be more suitable for single-die

release, although several of the processes have been scaled for wafer-level pro-

cesses. The techniques are extendable to other structural and sacriﬁcial material

combinations.

8.7.6 Examples: Sacriﬁcial Layer Removal and Structural

Layer Release

8.7.6.1 Example 1: Fine-Grain Stress-Controlled Polysilicon with an Oxide

Sacriﬁcial Layer

A2.0µm-thick ﬁne-grain stress-controlled polysilicon ﬁlm is deposited on a

1.5 µm-thick thermally grown oxide and annealed. The polysilicon is patterned and

etched, then undercut with concentrated HF etchant (49%) for 10 min to undercut

about 10 µm on each side of the patterned polysilicon, resulting in freestanding

cantilevered and doubly supported sections of polysilicon that are 20 µm wide. The

HF is removed with a dilution rinse where DI water is ﬂushed into the etch beaker

to dilute the etchant without removing the wafer. The wafer is dried with a nitrogen

gun, and high-stiffness beams and shells become freestanding.

8.7.6.2 Example 2: Poly-SiGe on a Patterned Oxide/Nitride Laminate

A1.0µm layer of borophosphosilicate glass (BPSG) i s deposited on a 500 Å thick

layer of silicon nitride on a silicon wafer. The bilaminate layer is patterned and

etched to expose anchor points. A 2.0 µm-thick SiGe polysilicon ﬁlm is deposited

8 MEMS Wet-Etch Processes and Procedures 621

Table 8.34 Rinse liquid removal processes

Material

Removal

rate (Å/s) Rinse liquid Remarks and references

1 Polysilicon

microstructures on

O Freeze-sublimation drying; also sublimation drying; dilution rinse, set

wafer horizontally with rinse water on top into roughing pump

vacuum system; self-freezes when pumping; sublimates free with

time; can be destructive due to water expansion when freezing; may

need thermal isolation [578]

2 Polysilicon

microstructures on

O:Methanol Freeze-sublimation drying; set wafer horizontally with rinse solution

on top into roughing pump vacuum system; self-freezes when

pumping; sublimates free with time; less destructive t han water;

may need thermal isolation [579]

3 Polysilicon

microstructures on

t-Butyl alcohol t-Butyl alcohol freeze-sublimation drying; displace rinse water with

IPA, transfer rapidly to liquid t-butyl alcohol (>26

◦

C), freeze in

refrigerator, then sublimate in vacuum pumping system [580]

4 Polysilicon

microstructures on

Cyclohexane Freeze-sublimation drying; dilution DI water rinse, add IPA and

transfer wafer to IPA bath, transfer to cyclohexane bath, freeze

(<5

◦

C) on Peltier cooler, then sublimate with N

gas ﬂow [581]

5 Polysilicon

microstructures on

Carbon dioxide

(CO

)

Supercritical CO

drying; dilution rinse, transfer to methanol bath,

replace methanol with liquid CO

(∼17

◦

Cat∼800 psi), increase

chamber pressure above 1350 psi as temperature is brought above

◦

C; retain temperature while venting CO

[576, 582]

6 Polysilicon

microstructures on

Octadecyltrichloro-

silane

(OTS)

Self-assembled monolayer (SAM) coating and drying; 0.02 M

solution in 5:1 hexadecane:CCl

mixture; HF etch, 15-min dilution

rinse, NH

OH:H

O 1:1:5 for 5 min at 70

◦

C, 10-min DI water

rinse, 5-min methanol bath, 15-min methanol, 5-min CCl

bath,

15-min CCl

, 5-min OTS solution, 5-min CCl

, 15-min CCl

5-min methanol, 15-min methanol, then air dry with IR lamp; stable

to 225

◦

C[583, 584]

622 D.W. Burns

Table 8.34 (continued)

Material

Removal

rate (Å/s) Rinse liquid Remarks and references

7 Polysilicon

microstructures on

Perﬂuorodecyltri-

chlorosilane

(FDTS)

Self-assembled monolayer (SAM) coating and drying; 0.001 M

solution in iso-octane; HF etch, 10-min DI water rinse, 15-min

(30 wt%) soak, 5-min H

O rinse, 5-min IPA rinse,

2 × 5 - min iso-octane rinses, 10-min FDTS solution in N

drybox,

2 × 5 - min iso-octane rinses, 2 × 5 - min IPA rinses, 5-min DI

water rinse, air dry; stable to 400

◦

C[585]

8 Polysilicon

microstructures on

Dichlorodimethyl-

silane

(DDMS)

Self-assembled monolayer (SAM) coating and drying; 0.001 M

solution in iso-octane; HF etch, 5 × 2-min DI rinses, 10-min

(30 wt%) soak, 1-1/2 min IPA wash and soak, 1-1/2 min

iso-octane wash and soak, 10-min DDMS solution, 2-1/2 min

iso-octane wash and soak, 1-min hot-plate dry, all in N

-ﬁlled glove

box at room temperature; stable to 400–450

◦

C in air; vapor-phase

variants available [586, 587]

9 Polysilicon

microstructures on

Polydiphenylsiloxane

(PDPS)

470–485

◦

C; WASA (wafer anti-stiction agent) coating;

silanol-terminated PDPS; evacuated N

-backﬁlled box oven; also

octaphenylcyclotetrasiloxane or mix with cyclic diphenylsiloxane;

25–45 min [588]

8 MEMS Wet-Etch Processes and Procedures 623

on the wafer and annealed. Buffered HF(6:1) is used to sacriﬁcially etch the BPSG

layer through an array of 4 µm-square holes in freestanding portions of the SiGe

layer and leave the nitride layer relatively intact. The wafer is placed into successive

beakers of methanol and then into a critical-point dryer (CPD) where the solvent is

displaced with liquid CO

under pressure. The pressure and temperature are raised

above the critical point and the chamber is vented while maintaining the temperature

above the critical point temperature, and the structure becomes free standing.

8.7.6.3 Example 3: Silicon Nitride on a Polysilicon Sacriﬁcial Layer

A1.0µm-thick layer of silicon-rich, stress-compensated silicon nitride is deposited

on a rough-textured polysilicon ﬁlm, patterned, and etched. The underlying polysil-

icon sacriﬁcial layer is removed in a wet etchant comprising sulfuric, nitric, and

acetic acids in a 2:3:2 ratio at room temperature. Standard dump-rinse and spin–dry

procedures are used for the small aspect-ratio structures.

8.7.6.4 Example 4: Aluminum on Photoresist

A2-µm thick layer of aluminum is e-beam evaporated onto a patterned layer of

1-µm thick photoresist. The aluminum is patterned and etched, and the photoresist

is solvent etched in acetone for 10 min to free the 60 µm-wide aluminum structures.

The structures are immersed in a rinse beaker with IPA for 5 min, then carefully

dried with a nitrogen gun.

8.8 Porous Silicon Formation with Wet Chemistry

With the application of suitably applied voltages, current, and in some cases external

light, silicon can be selectively etched into highly porous material using a hydroﬂu-

oric acid etchant. The transformed material retains its initial crystalline orientation,

along with hydrided surfaces and a spongelike or sometimes fractal pore structure.

The porous silicon can be further oxidized or etched, which can occur quite rapidly

due to the large surface area of the porous material. The porous layer can support

the deposition of additional ﬁlms such as epitaxially grown silicon as the outer pores

become plugged and provide a surface for further processing [589, 590].

Porous silicon can be formed by chemical staining etchants, although it is gen-

erally formed using dilute mixtures of hydroﬂuoric acid and either water or alcohol

in an electrochemical etch that is driven with an external power supply. Unmasked

portions of a silicon wafer are electrochemically etched with controllable pore sizes

and depths depending on the dopant type, dopant level, current density, and etchant

concentration, among other factors. Silicon surfaces exposed to the etchant are trans-

formed into porous silicon as the bulk silicon is etched. Prestructured substrates with

pyramidal etch pits or etched detents can cause pore initiation from the pit tip, fol-

lowed by pore formation perpendicular to the wafer surface a distance of several

hundred microns or more with continued application of current. Application of light