Ghodssi R., Lin P., MEMS Materials and Processes Handbook

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604 D.W. Burns

Etch

Bath

Etchant

Patterned

Wafers

Thin-Film

Etch Stop

Fig. 8.15 Thin-ﬁlm etch

stops for a nisotropic silicon

etching use one or more

etch-resistant layers on both

sides of the wafer, with one

side patterned. As the etch is

completed, the etch-stop layer

becomes free standing

squares on the bottom sides to expose 1–10  cm n-type (100) silicon surfaces.

A KOH-based etchant was selected for its high etching speed over a TMAH etchant.

After a 10-s predip into DHF etchant (10:1), the wafers are inserted with a Teﬂon

holder into a 30% KOH etchant at 90

◦

C in a double-wall quartz etch bath to remove

500 µm of silicon at a rate of 135 µm/h, taking about 3

h. A reﬂux condenser is

used on the etch ﬂask to contain and condense evaporated water and etchant vapors.

The etch stops automatically on the buried oxide, although the wafers are inspected

visually at the estimated etch time to show nearly complete clearing and then rein-

serted for another 10 min of overetch. The wafers are rinsed in DI water for 10 min

in a cascade-style rinse with a polypropylene tube to inject water carefully under

the wafers, then blown dry with nitrogen. The remaining nitride is stripped off in

hot phosphoric acid. The masking oxide and exposed portions of the buried oxide

are subsequently removed in concentrated HF etchant (49%) for 2 min to expose

tethered portions of a galvanically actuated micromirror. The wafers are carefully

rinsed and dried, then diced between two sheets of dicing tape.

8.6.8.2 Example 2: Heavy Boron-Doped Etch Stop

A2µm-thick p-type epitaxial layer with a high boron concentration of 1.0 × 10

–3

is grown epitaxially on a 1–10  cm p-type (100) silicon wafer. A 1.5 µm-

thick layer of low-temperature oxide is deposited on both sides of the wafer and

patterned on the bottomside. The 525 µm-thick wafer is inserted into EDP type F

etchant at 115

◦

Cfor6

h to remove exposed portions of the substrate and stop on

the p

epi layer. The oxide is stripped in a commercially available 6:1 buffered

oxide etch for about 12 min to free up a heater and sense elements for a mass air

ﬂow sensor.

8.6.8.3 Example 3: Electrochemical Etch Stop

A CMOS wafer with a p-type substrate and active circuitry in 5 µm-deep n-wells has

aluminum bond pads. Portions of the substrate around designated n-wells on each

die have exposed silicon from a semicustom masking and etching step performed at

the end of standard CMOS processing. The wafer is inserted into a special ﬁxture

that protects the sides and back of the wafer while allowing electrical connections

8 MEMS Wet-Etch Processes and Procedures 605

Table 8.30 Thin-ﬁlm etch stops for anisotropic silicon etching

Material

Etch rate

selectivity Etchant Remarks and references

1 Aluminum

(Al)

1:12

3:2

Good

1:1

3300:1

KOH(30 wt%)

OH(3.7 wt%)

OH(doped)

TMAH(22 wt%)

TMAH(doped)

◦

C; etches Si(100) ∼180 Å/s [28]

◦

C; etches Si(100) ∼65 Å/s [460]

◦

C; 0.1 g/l Si added [460]

◦

C; etches Si(100) ∼165 Å/s [465]

◦

C; 75 g/l Si added [465]

2 Chrome (Cr) 260:1

Good

KOH(30 wt%)

OH(3.7 wt%)

◦

C; etches Si(100) ∼180 Å/s [28]

◦

C; etches Si(100) ∼65 Å/s [460]

3 Copper (Cu) OK KOH(30 wt%) 80

◦

C; etches Si(100) ∼180 Å/s; thickens [28]

4 Gold (Au) Good

Good

EDP(EPW)

KOH(30 wt%)

OH(3.7 wt%)

110

◦

C; etches Si(100) ∼140 Å/s [442]

◦

C; etches Si(100) ∼180 Å/s; Au/Cr [28]

◦

C; etches Si(100) ∼65 Å/s [460]

5 Molybdenum

(Mo)

Good KOH(30 wt%) 80

◦

C; etches Si(100) ∼180 Å/s [28]

6 Nickel (Ni) Good KOH(30 wt%) 80

◦

C; etches Si(100) ∼180 Å/s [28]

7 Niobium

(Nb)

340:1 KOH(30 wt%) 80

◦

C; etches Si(100) ∼180 Å/s [28]

8 Palladium

(Pd)

Good KOH(30 wt%) 80

◦

C; etches Si(100) ∼180 Å/s [28]

9 Parylene

(Parylene

2600:1 KOH(30 wt%) 80

◦

C; etches Si(100) ∼180 Å/s [28]

10 Photoresist

(PR)

1:16 KOH(30 wt%) 80

◦

C; etches Si(100) ∼180 Å/s [28]

11 Platinum (Pt) Good KOH(30 wt%) 80

◦

C; etches Si(100) ∼180 Å/s [28]

12 Polyimide

(PI)

OK KOH(30 wt%) 80

◦

C; etches Si(100) ∼180 Å/s; thickens [28]

13 Silicides Generally resistant to aqueous alkali etchants; see Table 8.20 [127]

606 D.W. Burns

Table 8.30 (continued)

Material

Etch rate

selectivity Etchant Remarks and references

14 Silicon, poly

(Si-poly),

boron

doped at 4

× 10

–3

)

100:1 TMAH(22 wt%) 90

◦

C; etches Si(100) ∼165 Å/s [465]

15 Silicon–

germanium

(SiGe),

(100)

650:1

1200:1

240:1

155:1

EDP(EPW)

KOH(11/3 wt%)

TMAH(2 wt%)

TMAH(25 wt%)

◦

C; etches Si(100) ∼180 Å/s [476]

◦

C; etches Si(100) ∼165 Å/s [476]

◦

C; etches Si(100) ∼180 Å/s [476]

◦

C; etches Si(100) ∼70 Å/s [476]

16 Silicon

dioxide

(SiO

thermal

2500:1

140:1

9600:1

5000:1

EDP(EPW)

KOH(30 wt%)

OH(3.7 wt%)

TMAH(22 wt%)

110

◦

C; etches Si(100) ∼140 Å/s [442]

◦

C; etches Si(100) ∼180 Å/s [28]

◦

C; etches Si(100) ∼65 Å/s [461]

◦

C; etches Si(100) ∼165 Å/s [465]

17 Silicon

dioxide

(SiO

LTO

115:1

8300:1

EDP(EPW)

KOH(30 wt%)

OH(3.7 wt%)

110

◦

C; etches Si(100) ∼140 Å/s [442]

◦

C; etches Si(100) ∼180 Å/s [28]

◦

C; etches Si(100) ∼65 Å/s [461]

18 Silicon

nitride

(Si

)

Good

21000:1

Good

EDP(EPW)

KOH(30 wt%)

OH(3.7 wt%)

TMAH(22 wt%)

110

◦

C; etches Si(100) ∼140 Å/s [442]

◦

C; etches Si(100) ∼180 Å/s [28]

◦

C; etches Si(100) ∼65 Å/s [461]

◦

C; etches Si(100) ∼165 Å/s [465]

19 Silver (Ag) OK KOH(30 wt%) 80

◦

C; etches Si(100) ∼180 Å/s; thickens [28]

20 Tantalum (Ta) Good

390:1

Good

EDP(EPW)

KOH(30 wt%)

OH(3.7 wt%)

110

◦

C; etches Si(100) ∼140 Å/s [442]

◦

C; etches Si(100) ∼180 Å/s [28]

◦

C; etches Si(100) ∼65 Å/s [461]

21 Titanium (Ti) OK

Good

KOH

OH(3.7 wt%)

◦

C; etches Si(100) ∼180 Å/s; softens [28]

◦

C; etches Si(100) ∼65 Å/s [461]

8 MEMS Wet-Etch Processes and Procedures 607

Table 8.30 (continued)

Material

Etch rate

selectivity Etchant Remarks and references

22 Titanium-

tungsten

(TiW)

7:2 KOH(30 wt%) 80

◦

C; etches Si(100) ∼180 Å/s [28]

23 Tungsten (W) Good KOH(30 wt%) 80

◦

C; etches Si(100) ∼180 Å/s [28]

24 Vanadium

(V)

90:1 KOH(30 wt%) 80

◦

C; etches Si(100) ∼180 Å/s [28]

608 D.W. Burns

to bond pads that are internally connected to the substrate and to the designated n-

wells from the exposed front side. A 1-L solution of 5% TMAH etchant in water

is freshly mixed with 38 g of silicic acid to reduce aluminum attack and 7 g of

ammonium persulfate (AP) to decrease surface roughness, then heated to 80

◦

Cina

quartz etch bath with a quartz reﬂux condenser.

Using Teﬂon-coated wire and a four-terminal electrochemical etch conﬁguration,

the p-substrate is biased near the open-circuit potential at –1.5 V with respect to an

Ag/AgCl reference electrode in the solution and the designated n-wells are reverse

biased at +0.7 V with respect to the p-substrate. The ﬁxture is immersed into the

etching solution, and etched for 1

h (160 Å/s) to produce a self-limiting 100 µm-

deep v-grooved cavity with (111)-oriented ﬂanks while undercutting the 100 µm

by 50 µm designated n-wells. The oxide etches a total of 120 Å (0.019 Å/s) and

the aluminum etches a total of 80 Å (0.0125 Å/s). The wafer is carefully rinsed and

dried, and then diced with dicing tape on both sides of the wafer. Prior to wirebond-

ing, the dicing tape above each die is carefully peeled back to avoid breaking the

thermally isolated structures [511, 512].

8.7 Sacriﬁcial Layer Etching

Sacriﬁcial layers, structural layers, and a highly selective wet etch combine to form

freestanding microstructures for a wide variety of devices including cantilevered

beams, resonators, pressure sensors, accelerometers, gyroscopes, ﬂow sensors, IR

detectors, inkjet heads, microphones, optical switches, microdisplays, microﬂuidic

devices, microtips, electrical probes, bio-MEMS and RF-MEMS devices, micro fuel

cells, and energy harvesting devices. Sacriﬁcial layer etching is the selective removal

of thin ﬁlms or portions of the substrate under structural layers that allows the struc-

tural layers to become freestanding, attached to the substrate at only predeﬁned

locations. Cantilevered beams, for example, can be selectively undercut to make the

beam freestanding at all but the base. Doubly supported beams are attached at each

of two ends and freestanding elsewhere, and freestanding membranes, plates and

shells are attached to the substrate at one or more sides. Figure 8.16 shows a can-

tilevered geometry where the freestanding structure is undercut with a timed etch

and another where the sacriﬁcial etching is self-stopping. The self-stopping process

architecture allows structures with different undercut lengths to be fabricated on

the same wafer at the s ame time, and provides the process engineer with a robust

etching procedure.

Lateral etching with a liquid or gaseous etchant allows the sacriﬁcial layer to

be removed while leaving the structural layer intact. Extensive lateral etching is

generally difﬁcult to achieve with a dry plasma or RIE etch, whereas selective liq-

uid etchants with their relatively small mean free path can enter very narrow and

tortuous paths to efﬁciently remove sacriﬁcial layers.

Structural layers are generally several micrometers thick and sacriﬁcial layers can

be several hundred angstroms to a hundred microns or more thick. The etchant must

8 MEMS Wet-Etch Processes and Procedures 609

a) b)

c) d)

Fig. 8.16 Surface-micromachined structures can be made freestanding by removal of an under-

lying sacriﬁcial layer or portion of the substrate with extensive lateral etching by a selective wet

etchant. (a) A cantilevered beam, attached to the substrate through a support at the base, is freed

up with a timed etch and a single masking step. (b) A cantilevered beam, attached to the substrate

at the base through a patterned opening in the sacriﬁcial layer, is freed up with a self-stopping etch

using two masking steps. (c) A cantilevered beam, formed from the passivation layer, is freed up

with a timed or a self-limiting anisotropic substrate etch using only one masking step. (d) A can-

tilevered beam, attached to the substrate at the base through a patterned opening in a passivation

layer, is freed up with a selective substrate etch using a total of three masking steps

be very selective to effectively remove the sacriﬁcial layer and leave the structural

layers intact without much if any thinning. A high etch selectivity implies that the

sacriﬁcial layers are etched much faster than the structural layers and other layers

that support the structural layers.

The etch rate and etch selectivity combine with the thickness of the structural

layer to determine the maximum amount of time that the die or wafers can be in the

etchant. An etchant with high selectivity allows the devices to be in the etchant for

an extended time and provides signiﬁcant overetching capability. In cases where the

etch time is unduly limited, the user generally can make adjustments to the process

or to the device design. The process may be adjusted by choosing a more selective

etch process, using more selective materials, or incorporating an etch accelerator

layer. Design alterations may limit the amount of time required in the etchant, for

example, by limiting the undercut distance with narrower structural features or by

strategically placing small openings in the structural features so that the etchant has

local access to the sacriﬁcial layer.

Certain devices require an isolation layer between the sacriﬁcial layer and sub-

strate, such as an LPCVD silicon nitride layer for electrical isolation. The etchant

must similarly be selective over any isolation or passivation layers.

As surface-micromachined devices can be quite fragile after sacriﬁcial etching,

the etching and drying steps are generally placed late in the process sequence, and

careful handling procedures may be needed to avoid unnecessary contact with or

undue forces on the microstructures during subsequent dicing and packaging steps.

610 D.W. Burns

For particularly fragile structures, special rinse liquid removal techniques may need

to be adopted. Devices subject to release stiction or in-use stiction may incor-

porate a coating such as a self-assembled monolayer (SAM) into the ﬁnal rinse

procedure.

8.7.1 Sacriﬁcial Layer Removal Techniques

Wet chemical etching remains predominant in removal of sacriﬁcial layers for

MEMS devices. A room-temperature etchant using standard cleanroom chemicals

and an etch process with abundant overetch capability followed by standard DI

water rinse procedures may be satisfactory for relatively stiff structures. For exam-

ple, a buffered HF etch followed by a set of dump rinses and a spin–dry sequence

may be used to free long, narrow polysilicon shells with no special handling

considerations.

For fragile structures, wet chemical etching may be augmented with special pro-

cedures to prevent breakage of the microstructure and reduce yield losses due to

stiction from surface tension, van der Waals forces, and solid-residue bridging.

Techniques such as freeze-sublimation drying or critical-point drying can be applied

that prevent the microstructure from coming into surface-to-surface contact with the

substrate and avoid opportunities for unwanted adherence from stiction.

Low surface-tension coatings may improve the process yield and device reli-

ability. These may be applied as part of the ﬁnal drying sequence, or be applied

postrelease yet prior to packaging.

Dry vapor etching techniques can successfully free microstructures. By avoiding

contact with any liquid, the capillary forces that tend to drive the microstructure into

contact with the substrate during drying are effectively nulliﬁed. Vapor HF is one

example of a dry release technique that can be done in specially designed ﬁxtures

[513]. Controlled gaseous xenon diﬂuoride etching can selectively remove exposed

portions of the silicon substrate and polysilicon layers to release metal and dielectric

structures using a vapor phase etch without any liquids or plasmas [514–518]. With

high selectivity to photoresist, silicon dioxide, silicon nitride, and aluminum, this

isotropic etch can be highly effective for integrated MEMS devices to avoid issues

related to stiction and provide compatibility with active on-chip devices. Under var-

ious conditions of pressure and temperature, other vapor etchants may be used to

etch silicon including Cl

O, H

S, HBr, HCl, HI, HI-HF, and SF

[25]. Dry

plasma etching with SF

and other etchants has been shown to be effective i n selec-

tively etching portions of a silicon substrate or a polysilicon sacriﬁcial layer with

moderate selectivity to oxide [519, 520].

Other sacriﬁcial layer removal techniques include plasma or reactive ion etching

of photoresist or other sacriﬁcial materials to free up structural layers selectively. For

example, an e-beam evaporated aluminum ﬁlm on top of photoresist or polyimide

can be patterned and etched, then the organic layer removed in an oxygen plasma

[521, 522].

8 MEMS Wet-Etch Processes and Procedures 611

8.7.2 Sacriﬁcial Oxide Removal for Polysilicon Microstructures

A predominant number of devices use deposited polysilicon thin ﬁlms as the struc-

tural layer and silicon dioxide as the sacriﬁcial layer, in part because the polysilicon

ﬁlms are IC compatible and structurally well-matched with the substrate, in part

because the oxide layer is also IC compatible, and in part because hydroﬂuoric-

based etchants have an extremely high selectivity to oxide over polysilicon. Lateral

etches may exceed 500 µm, and the HF-based etchants can clear sacriﬁcial oxides

fewer than 100 Å thick with little impediment [523]. Polysilicon ﬁlms for struc-

tural layers may be deposited as ﬁne-grained, stress-controlled ﬁlms. They may

be codeposited with germanium as SiGe ﬁlms, or doped in situ. Epitaxial pro-

cesses for epi-poly, sputtered poly, and even amorphous silicon may also serve as

structural layers. The underlying sacriﬁcial oxide may be thermally grown offer-

ing the highest quality yet the slowest etching oxide. Low-temperature CVD oxides

(LTO), doped oxides (BSG, PSG, and BPSG), sputtered oxides and spin-on glass

(SOG) can be effectively used as sacriﬁcial layers and etch much faster to pro-

vide shorter sacriﬁcial etch times. A fast-etching oxide over a slow-etching thermal

oxide serves as an etch accelerator layer to decrease the total etch time. A bil-

aminate layer such as oxide over silicon nitride allows the oxide to be removed

with only minor etching of the nitride that may continue to serve as a buffer or

isolation layer. Table 8.31 shows a progression of removal techniques for oxide

sacriﬁcial layers and polysilicon microstructures with various oxide types and

etchants.

8.7.3 Alternative Sacriﬁcial and Structural Layer Combinations

Deposited polysilicon, either LPCVD, PECVD, sputtered, or epi-poly, can serve

alternatively as a sacriﬁcial layer for oxide or nitride freestanding structures. Metals

such as aluminum that are readily etched also may be used as sacriﬁcial layers.

Polymers including photoresist with overlying deposited layers of e-beam or sput-

tered metals have been used as sacriﬁcial layers. Various alternative sacriﬁcial layers

and structural layers for MEMS devices have been proposed or explored, including

structural layers of chromium, copper, gold, molybdenum, nickel–chrome, niobium,

palladium, platinum, polyimide, silicon nitride, silver, tantalum, titanium–tungsten,

tungsten, and vanadium, with sacriﬁcial layers s uch as deposited unannealed PSG

with an HF etchant [28].

Several authors have compiled collections of actual and prospective structural

and sacriﬁcial layers based largely on silicon substrates and silicon semiconductor

manufacturing [28, 78, 408]. Nonsilicon systems such as III-V compounds also have

seen development of a number of successful sacriﬁcial layers, structural layers, and

highly selective etchants and have been itemized elsewhere [532]. Table 8.32 lists a

number of sacriﬁcial and structural layer combinations with particular emphasis on

etchants commonly available in development and manufacturing sites.

612 D.W. Burns

Table 8.31 Sacriﬁcial layer removal for polysilicon microstructures

Structural

layer/sacriﬁcial

layer

Etch rate

(Å/s) Etchant Remarks and references

1 Polysilicon (Si,

poly)/oxide

(SiO

, CVD)

BHF Room temperature; BHF etchant; 640

◦

polysilicon deposition; 1100

◦

C anneal;

0.23–2.3 µm thick; 0.55–3.5 µmgap;

25–200 µm long cantilevers;

15–60 µm wide; 100–500 µm bridges;

CVD oxide sacriﬁcial layers; implanted

PSG oxide etch accelerator layer;

compressive ﬁlms [524]

2 Polysilicon (Si,

poly)/oxide

(SiO

thermal)

HF(49%)

undiluted

Room temperature; HF etchant (49 wt%);

635

◦

C polysilicon deposition;

high-temperature anneal; 2.0 µmthick;

1.0 µm gap; 200 µm × 200 µm plates;

thermal oxide sacriﬁcial layer; reactive

sealing (vacuum sealing) with oxide or

poly; 0.01% compressive strain after

annealing [525]

3 Polysilicon (Si,

poly)/oxide

(SiO

, PSG)

5400 HF(49%)

undiluted

Room temperature; HF etchant (49 wt%);

950

◦

C anneal of PSG sacriﬁcial layer;

lateral etch rate for PSG(8 wt%); etch

rate slows after ∼280 µm of undercut;

etch rate lessens for HF dilution and

lower phosphorus content [526, 527]

4 Polysilicon (Si,

poly)/oxide

(SiO

thermal)

250 HF(73%)

undiluted

Room temperature; HF etchant (49 wt%);

etches slightly Al (0.35 Å/s) with 680:1

selectivity (40:1 selectivity with pad

etch); add glycerol to BHF for 170:1

selectivity over Al; etches SiO

(300 Å/s) in HF(73%):IPA 2:1; avoid

water rinsing [93]

5 Polysilicon (Si,

poly)/oxide

(SiO

, SOG)

BHF Room temperature; BHF etchant; 425

◦

cure of spin-on glass [528]

6 Polysilicon (Si,

poly)/oxide

(SiO

thermal)

45 HF(49%):

1:1, vapor

◦

C; vapor HF etchant; sample at 31.5

◦

(critical) positioned in vapor above HF

bath; avoid condensation; avoid

substrate overheating [529, 530]

7 Polysilicon (Si,

poly)/oxide

(SiO

, PSG)

48 HF(49%)

undiluted,

vapor

◦

C; vapor HF etchant; bubbled N

through HF; slight vacuum; etches

Al(0.5%Cu) (0.005 Å/s), SiO

-thermal

(2.5 Å/s), Ti (0.03 Å/s), TiN (0.01 Å/s)

[531]

8 MEMS Wet-Etch Processes and Procedures 613

Table 8.32 Sacriﬁcial layer removal for alternative structural and sacriﬁcial layer combinations

Structural

layer/sacriﬁcial layer

Etch rate

(Å/s) Etchant Remarks and references

1 Aluminum (Al)/silicon

(Si)

165–500 XeF

(vapor)

4Torr

Room temperature; XeF

vapor etchant; aluminum traces and oxide

encapsulated polysilicon; doesn’t signiﬁcantly etch Al, PR, Si3N

SiO

; loading and surface preparation effects [514]

2 Aluminum (Al)/oxide

(SiO

, SOG)

70 Ammonium ﬂuoride,

acetic acid

Room temperature; pad etchant; etches Al (0.5 Å/s); DI water rinse

[90, 533]

3 Aluminum gallium

arsenide

(AlGaAs)/gallium

arsenide (GaAs)

650 NH

OH(29%):

(30%)

1:30

◦

C; Al

1−x

As structural layer with x > 0.4; 650:1 selectivity at

x = 0.6 [196]

4 Aluminum nitride

(AlN)/oxide (SiO

PSG)

165 NH

F(40%):Acetic:

2:2:1

Room temperature; structural layer includes Al and Pt/Ta electrodes;

DI water rinse [534]

5 Gallium arsenide

(GaAs)/AlGaAs

HF(49%):H

1:4

Room temperature; DHF etchant (4:1); GaAs substrate and structural

layer; Al

1−x

As sacriﬁcial layer with x > 0.5 [532]

6 Germanium (Ge,

poly)/oxide (SiO

LTO)

BHF Room temperature; BHF etchant; also etches in HF etchant; 400

◦

LPCVD Ge deposition; poly-Ge can be etched in hot

OH(29%):H

(30%):H

O 1:1:5 at 500 Å/s or piranha [535]

7 Gold (Au)/aluminum

(Al)

◦

C gold electroplating; aluminum or copper sacriﬁcial layer [536]

8 Indium arsenide

(InAs)/aluminum

antimonide (AlSb)

HF(49%):H

1:20

Room temperature; DHF etchant (20:1); InAs structural layer;

aluminum antimonide sacriﬁcial layer; doesn’t signiﬁcantly etch

GaAs [130]

9 Indium gallium arsenide

phosphide

(InGaAsP)/indium

gallium arsenide

(InGaAs)

HF(49%):

(30%)H

1:1:8

Room temperature; structural layer is predominantly InP; sacriﬁcial

layer is In

0.53

0.47

As; DI water rinse [537]