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634 D.W. Burns

Table 8.39 Silicon dislocation delineation etchants and etch processes – II

Material

Etch rate

(Å/s) Etchant Remarks and references

1 Silicon (Si), (100) 300 HF(49%):CrO

200 mL:10 g: 100

Room temperature; Schimmel etchant (1 M CrO

in H

O);

nonstandard chemical; dislocations; 5–10 min; dilute with H

Oby

50% for heavily doped Si; circular etch pits in Si(100) and Si(111)

[622, 623]

2 Silicon (Si), (100),

(110), (111)

250 HF(49%):CrO

100 mL:15 g: 100

Room temperature; Yang etchant (1.5 M CrO

in H

O); preferential

etching of silicon surface and stacking defects; 2–15 min;

well-deﬁned etch pits [624]

3 Silicon (Si), (111) 210 HF(49%):CrO

200 mL:50 g: 100

Room temperature; Sirtl etchant (5 M CrO

in H

O); favors (111)

surfaces; ineffective for Si(100); preferential etching of silicon

defects; ∼3 min; 5–15 s for cross-sectioning; mix fresh;

well-deﬁned etch pits [45, 76, 624]

4 Silicon (Si), (100),

(111)

165 HF(49%):

CrO

(5 M):

Cu(NO

)

HNO

(70%):Acetic:

60 mL:30 mL:2 g:

30 mL:60 mL:60

Room temperature; Wright etchant; combine 15 g CrO

with 30 mL

O for 5 M solution; stacking faults, dislocations, swirls and

striations; 1–5 min for crystalline defects; 5–10 s for

cross-sectioning; dopant-sensitive [45, 625]

5 Silicon (Si), (100) or

(111)

HF, others 25

◦

C; Transene Wright etchant; reveals crystal dislocations, stacking

faults, swirls, striations and slip lines; <100> and <111>

orientations; p and n dopants; polyethylene or polypropylene tank

[626]

8 MEMS Wet-Etch Processes and Procedures 635

Table 8.39 (continued)

Material

Etch rate

(Å/s) Etchant Remarks and references

6 Silicon (Si), (100),

(111)

830 HF(49%):

Cu(NO

)

HNO

(70%):Acetic:

36 mL:1 g:25 mL:

18 mL:21 mL

◦

C; Chandler etchant (MEMC etchant); dislocations, slip, twins,

and stacking faults [627]

7 Silicon (Si), (100),

(110), (111)

250 HF(49%):K

200 mL:4.4 g: 100

25–30

◦

C; Secco etchant; K

(0.15 M in H

O); dislocations and

lattice defects; ∼20 min; ∼5 min with ultrasonic; hold sample

vertically; also polysilicon grain boundary etchant when used for

30 s at room temperature; dilute with 10 parts water for n-type

staining etchant [45]; mix fresh; circular etch pits in Si(100),

Si(111) [628]

636 D.W. Burns

Table 8.40 Grain-boundary delineation etchants and etch processes

Material

Etch

rate

(Å/s) Etchant Remarks and references

1 Aluminum

(Al)

(96%):

HF(49%):H

1:1:8

Room temperature; aluminum grain

boundary etchant; 35–40 s [45]

2 Silicon (Si),

poly

25 HF(49%):

HNO

(70%):Acetic

1:20:20

Room temperature; HNA etchant;

polysilicon grain boundary etchant;

∼30 s; illuminate and etch for 5–7 s

for cross-sectioning; mix fresh [45]

3 Silicon (Si),

poly

Wright etch:H

1:5

Room temperature; polysilicon grain

boundary etchant; 40 s [629]

8.9.2 Layer Delineation with Wet Etchants

Silicon, polysilicon, and layers of metals, oxides, and dielectrics and other mate-

rial stacks can be beveled by grinding and polishing to form an elongated surface

proﬁle representative of the layer depths of a sample, then stained and inspected to

determine thickness, crystallinity, dopant type, dopant concentration, and metallur-

gical junctions. Some etchants for delineating oxides of various types are found in

Table 8.41. These may be combined sequentially with dopant-sensitive etchants as

in Table 8.37 to highlight a variety of features of interest in a device. Table 8.42

shows several etchants for revealing pinholes and other defects in oxide and nitride

passivation layers above deposited aluminum traces.

Table 8.41 Oxide layer delineation etchants and etch processes

Material

Etch

rate

(Å/s) Etchant Remarks and references

1 Silicon

dioxide

(SiO

(PSG)

over

SiO

220–

570

HF(49%):

HNO

(70%):H

3:2:60

◦

C; HNW etchant; phosphosilicate

glass (P

); etches SiO

(1.8 Å/s);

selectivity of 100:1 to 300:1 PSG over

SiO

[630]

2 Silicon

dioxide

(SiO

thermal

6NH

F(40%):Acetic:

1:1:1

Room temperature; AMS-5 etchant; oxide

etching or cross-sectioning; etches

doped, unannealed oxide up to 65 Å/s;

slower attack on Al; omit H

Ofor

further reduction in Al attack [45]

8 MEMS Wet-Etch Processes and Procedures 637

Table 8.42 Pinhole detection etchants and etch processes

Material

Etch

rate

(Å/s) Etchant Remarks and references

1 Aluminum

(Al), pas-

sivated

(96%)

undiluted

120

◦

C; pinhole detection; oxide or nitride

passivation l ayers over aluminum;

∼5min[45]

2 Aluminum

(Al), pas-

sivated

(85%):

HNO

(70%):H

80:8:38

◦

C; pinhole detection; oxide or nitride

passivation l ayers over aluminum;

2–5 min [45]

3 Aluminum

(Al), pas-

sivated

(85%):

HNO

(70%):Acetic:

80:5:5:10

Room temperature; PAN etchant; pinhole

detection; oxide or nitride passivation

layers over aluminum; 20–30 min [45]

8.9.3 Examples: Layer Delineation and Defect Determination

8.9.3.1 Example 1: Metallurgical Junction Determination

A test wafer is diced along a predetermined region containing a diffused n

runner

in a p-type substrate. A s ample including the region is potted onto a 3

◦

mounting

ﬁxture, then lapped and polished to expose the layers. A few drops of p–n junction

delineation etchant comprising concentrated HF, nitric, and acetic acids in a 1:3:10

combination is placed onto the sample in a bright light for 15 s. The sample is rinsed

in DI water and blown dry. Microscope inspection reveals a 1.0 µm-deep conductive

trace for a MEMS accelerometer with on-chip transistors [613, 631].

8.9.3.2 Example 2: Cross-Sectioning and Layer Delineation

An integrated CMOS and MEMS microphone die is attached with high-temperature

wax to a vertical polishing ﬁxture. After lapping and polishing, the die is structured

for 5 s in an AMS-5 oxide etchant to delineate the thermal and deposited oxides,

then structured for 3 s in a p–n junction etchant (97:3 HNO

:HF) to delineate the n-

doped regions. After rinsing and drying, an SEM shows deposited oxide and nitride

passivation layers, two layers of aluminum separated by an intermediate oxide, tung-

sten vias with TiN local interconnects, a polysilicon gate layer, a thick ﬁeld oxide,

a gate oxide, n

diffusions and source/drains, p

diffusions and source/drains, an

n-well, a p-well, and a p-type substrate associated with a twin-well CMOS process

[45, 631].

638 D.W. Burns

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