Ghodssi R., Lin P., MEMS Materials and Processes Handbook
Подождите немного. Документ загружается.
1164 M.A. Huff et al.
from older and out-of-date integrated circuit foundries or equipped with used tools
from equipment brokers.
It is also important to consider that MEMS production foundries are typically not
able to achieve the same economies of scale due to the specialized nature of each
MEMS device, application, and associated process technology. Therefore, much
thought must be put into the decision of whether to build and facilitate a dedicated
MEMS foundry. Important factors in this decision include the projected manufactur-
ing volume that is required to satisfy the market with the intended device product(s),
whether this production volume with the associated revenues and profits can cover
the costs of building and operating the facility, the potential ability of selling excess
foundry capacity, and, the ability and potential cost advantages gained by going
“fabless” and leveraging from an existing MEMS foundry production capability.
Each of these factors should be carefully and objectively examined before mak-
ing a decision. Although the option of selling excess capacity may sound inviting,
in reality it can be very difficult to find customers that can utilize and are willing
to purchase the excess production capacity of a foundry due to proprietary con-
cerns and other issues. On the other hand, although it also may sound very inviting
to outsource the production to an existing foundry, the problem is that significant
investments will often be needed in order to have the correct equipment set for
your specific MEMS manufacturing process technology installed at a foundry. This
means that either you will pay for such equipment, reducing the financial benefit of
outsourcing, or the foundry pays for the equipment and then recoups its costs by
raising the per-die costs. Risk that the foundry will have financial problems and go
out of business must also be considered. Clearly, selecting a suitable foundry and
negotiating an appropriate contract are vital to the financial success of an outsourced
MEMS product development.
We now examine the nonrecurring engineering costs of MEMS device devel-
opment. This t ask is also neither simple nor easy. First, the process sequence and
packaging method that will be employed should be well defined in order to estimate
the development costs. Assuming that this is the case, then the question becomes
one of defining whether any part of the process sequence can utilize existing and
already developed process modules and/or processing steps. If this is the case, then
the cost of running these process modules and/or processing steps will be avail-
able and can be added together to estimate the “developed” portion of the process
sequence. Note that there may be licensing fees associated with the use of another
party’s intellectual property (IP).
The next step is to figure out how much of the process sequence is “undevel-
oped” and how much effort and risk is involved in developing these portions of
the process sequence. The total of “developed” and “undeveloped” portions can
then be integrated into a viable process sequence. Typically, the portions of the pro-
cess sequence that need to be developed will require processing step development,
running partial sequence experiments (short-loop experiments), and process integra-
tion. In many cases, transferring process recipes from research-oriented equipment
(such as university fabs) to production tools in a manufacturing environment is best
considered as “undeveloped” because the differences in tool types and settings can
14 MEMS Process Integration 1165
be quite significant and may require significant time and effort to resolve. Estimating
the time and cost of these activities will require experienced MEMS fabricators.
A major reason for the difficulty in estimating these costs is the widely varying
difficulty and associated risk involved in developing a new processing step, process
module(s), and process sequence. That is, a process sequence that pushes the tech-
nology envelope will be inherently more risky and more expensive (and take longer)
to develop than one that does not. The determination of a process s equence’s risk
is something that requires a considerable amount of MEMS fabrication experience.
Previous demonstrations of a fabrication method are extremely helpful for reducing
process development risk, but it should also be noted that a published paper in an
academic journal touting the merits of a process sequence should be viewed with
a fair amount of skepticism with respect to statements regarding “high yield” and
“manufacturability.”
In addition to the risk level, another large determinant of NRE development cost
will be whether the MEMS device is based on an integrated process sequence (i.e.,
MEMS merged with microelectronics on the same substrate). As a general rule,
the cost to develop an integrated process sequence will be far more expensive than
the development of a nonintegrated process sequence. As an example, the cost to
develop the few integrated process technologies in current production was in most
cases on the order of $100 M or more.
The last major determinant of NRE development cost will be the number of pro-
cessing steps in the process sequence and the difficulty in integrating those s teps into
a viable process sequence. To date, most nonintegrated MEMS process technologies
have required on the order of a few $10 Ms or more to develop to production level
capability. Moreover, the average length of development time from taking a MEMS
device from concept to a manufacturable product has often been over 5 years. It is
important to note that both the total time and cost of MEMS development can be sig-
nificantly reduced by leveraging from existing process technologies. These figures
are meant as useful guidance on MEMS development costs, not as exact estimations
that are applicable to every scenario or situation. An accurate estimate of NRE cost
to develop a fully or partially customized MEMS process sequence requires knowl-
edge of the specifics of the process sequence to be employed, access to costing
information (preferably from multiple foundries and sources), experienced MEMS
developers, and if possible, software to automate the ability to change important
variables such as wafer sizes, tools, and so on. Most of these resources and capa-
bilities are proprietary and are not generally available free of charge to the public.
However, there are organizations that have these resources and they can provide
these estimates as a service [98, 99].
The development costs of packaging, including assembly and testing, must also
be taken into account. As described above, MEMS packaging often requires a
unique and highly customized solution and therefore existing packaging approaches
may not be suitable. If this is the case, a customized packaging solution will
need to be developed. It is difficult to estimate the cost of packaging development
inasmuch as it can vary over such a large range. This is particularly true when spe-
cialized assembly, packaging, or testing equipment is not available and needs to
1166 M.A. Huff et al.
be developed. For example, for microfluidic inkjet printheads, the assembly and
packaging cost can be several times the chip cost. Therefore, it is advisable to
consult with an experienced and knowledgeable MEMS packaging technologist for
assistance in developing a plan and estimating these costs.
14.9.2 Production Cost Models
Production costs are a variable cost and as stated above are directly attributable
to the manufactured product and are proportional to the volume of product being
produced. The development of accurate cost estimates for the production of MEMS
devices and products is no easier a task to perform than for development. Although
the methods of estimating production costs for the integrated circuit industry are
fairly standardized and reasonably well developed, the same is not true for MEMS
production. That is, there are standardized cost models for integrated circuits that are
commonly used by industry, which typically estimate a cost per unit area (e.g., a few
cents per square millimeter) depending on the exact process technology employed
(e.g., 45 nm CMOS, etc.) and the volume involved. In contrast, the cost per area for
a MEMS device could range from essentially equivalent to that of ICs on the low
side to orders of magnitude more expensive on the high side.
Many of the same comments made with regard to estimating the development
costs are equally applicable to MEMS production. Specifically, it is very difficult
to develop cost models for “generic” MEMS processes that have a hope of being
generally applicable, inasmuch as there are no generic MEMS processes or process
technologies. That is, the cost to produce a MEMS device wafer is very dependent
on specific details of the fabrication process sequence. Equally important is that
the cost of production will also depend on the details of the fabrication facility’s
installed infrastructure, the production yield, the production volume, and the pro-
duction capacity utilization. For example, yields in IC manufacturing are routinely
above 90% once in high-volume production, whereas yields for MEMS produc-
tion are often considerably lower, even in volume production. Similarly, IC foundry
capacity utilization levels routinely run above 85%, whereas MEMS foundries often
run at much lower utilization levels. These factors all have a significant impact on
the cost of production, but can be very hard to estimate until the device is in a volume
production scenario. In addition to the device wafer costs, there are probe, assem-
bly, and test costs that are typically much larger than the wafer cost. In short, given
the wide range and diversity of MEMS processes, process technologies, packaging
approaches, assembly, and test methods, it is nearly impossible to provide a simple
methodology that allows production costs to be accurately estimated. Therefore, our
approach is to go through an illustrative example in the next section.
14.9.2.1 MEMS Hybrid Versus Integrated MEMS Production Cost
In this section we develop a cost estimate for the production of a MEMS device
that requires microelectronics. We examine the case where the IC die is assembled
in the same package as the MEMS (i.e., the hybrid approach) versus the case
14 MEMS Process Integration 1167
where the MEMS is integrated with the microelectronics (i.e., the integrated MEMS
approach). This example demonstrates how a cost analysis is performed, wherein the
key decision is whether a cost savings is gained by integrating the MEMS device
with electronics.
Production cost estimates are usually based on calculating the complete manu-
facturing cost of a packaged device, including any associated assembly and testing
costs. Typically, the starting point is to calculate the usable amount of area available
on the wafer, the number of die per wafer (which obviously depends on the size of
the die and wafer diameter that the die are made from), and the number of “accept-
able” or “usable” die per wafer (i.e., the production yield). Yields can be stated at
various points in the production, including after fabrication, after assembly, after
testing and packaging, and so on. The collective yield would be the product of each
of the yields of all parts of the manufacturing process. Once the number of yielded
die has been calculated, then taking the production cost of each wafer and dividing
by the number of yielded die allows the cost of each die to be calculated. Other cost
components such as mounting, packaging, and testing are then added to derive the
cost of a fully assembled, tested, and packaged die.
Table 14.3 shows a calculation of the usable area and die yielded in our example
for 150 mm diameter wafers wherein the blue fields are the values entered depend-
ing on the process, device type, and wafer size. Table 14.4 is the calculation of the
usable area and die yielded for 200 mm diameter wafers. In this analysis and both
Tables 14.3 and 14.4, the area of the CMOS die is varied from 0.5 to 4 mm
2
and the
MEMS die area is constant at 0.5 mm
2
. The other entries in this table are straight-
forward. The wafer edge exclusion is 3 mm for the CMOS wafers and 10 mm for
the MEMS wafers. This refers to the annular-shaped area that lies between where
the substrate is yielding acceptable devices and the actual edge of the wafer. The
dies are either square or rectangular and the wafer is circular, therefore there will
always be some wasted area at the edge of the substrate. This is independent of
wafer diameter. Most starting wafers are beveled at the edges to reduce breakage
during handling and this also results in some part of the substrate surface being
unusable.
The larger amount of edge exclusion for the MEMS wafer as compared to the
CMOS wafer is illustrative in MEMS fabrication wherein devices near the substrate
edge often do not yield due to process nonuniformities and large topologies. The
useful area is calculated by a simple calculation of (wafer radius [millimeters] –
wafer exclusion [millimeters])
2
× 3.14. This assumes that the MEMS chip area is
small compared to the wafer area such that the error associated with this “averaging”
is negligible. For example, the good MEMS die per 150 mm diameter wafer in the
first data column of Table 14.3, is equal to 13267/(0.5 + 0.05) ∗ 90% = 21, 709.
Also note that the MEMS bond pad area in this example is entered as a separate line
item (i.e., separate from the MEMS device area) in order to provide some flexibility
depending on the packaging approaches that are being considered (i.e., different
packaging approaches may require more or less bond pad area). Another reason
for considering the MEMS die bond as a separate line item is that this area is not
required in an integrated MEMS device.
1168 M.A. Huff et al.
Table 14.3 Calculation of the usable area for 150 mm diameter wafers
a
Calculation of number of die
Wafer diameter [D] mm Input D 150 150 150 150 150
CMOS wafer edge exclusion (without
chips) [CWE]
mm Input CWE 33333
MEMS wafer edge exclusion (without
chips) [MWE]
mm Input MWE 10 10 10 10 10
Useful CMOS wafer area for 150 mm wafer
[AreaC150]
mm
2
AreaC150 = pi
∗
(D/2 – CWE)ˆ2 16,278 16,278 16,278 16,278 16,278
Useful MEMS wafer area for 150 mm
wafer [AreaM150]
mm
2
AreaM150 = pi
∗
(D/2 – MWE)ˆ2 13,267 13,267 13,267 13,267 13,267
CMOS circuit area incl. outside bond pads
[CA]
mm
2
Input CA 0.5 1 2 3 4
MEMS area [MA] mm
2
Input MA 0.5 0.5 0.5 0.5 0.5
MEMS chip bond pads area [MBA] mm
2
Input MBA 0.05 0.05 0.05 0.05 0.05
Yield MEMS [YM] % Input YM 90.0% 90.0% 90.0% 90.0% 90.0%
Yield packaging and test [YPT] % Input YPT 96.0% 96.0% 96.0% 96.0% 96.0%
Yield CMOS (area dependent!) [YCMOS] % YCMOS = 1–(CA
∗
0.005) 99.8% 99.5% 99.0% 98.5% 98.0%
Yield Integrated MEMS [YieldIM] % YieldIM =
YM
∗
YCMOS
∗
0.85
76.3% 76.1% 75.7% 75.4% 75.0%
Good CMOS chips per 150 mm wafer
[NumC150]
# NumC150 = (AreaC150/CA)
∗
YCMOS
32,474 16,196 8057 5345 3988
Good MEMS chips per 150 mm wafer
[NumM150]
# NumM150 = [AreaM150/(MA +
MBA)]
∗
YM
21,709 21,709 21,709 21,709 21,709
Good integrated chips per 150 mm wafer
[NumIM150]
# NumIM150 = [AreaM150/(CA +
MA)]
∗
YieldIM
10,124 6732 4019 2856 2210
a
Using a MEMS-only, a CMOS-only, and an integrated MEMS (i.e., MEMS integrated with CMOS on the same substrate) process technology
14 MEMS Process Integration 1169
Table 14.4 Calculation of the usable area for 200 mm diameter wafers
a,b
Calculation of number of die
Wafer diameter [D] mm Input D 200 200 200 200 200
CMOS wafer edge exclusion (without
chips) [CWE]
mm Input CWE 33333
MEMS wafer edge exclusion (without
chips) [MWE]
mm Input MWE 10 10 10 10 10
Useful CMOS wafer area for 200 mm wafer
[AreaC200]
mm
2
AreaC200 = pi
∗
(D/2 – CWE)ˆ2 29,544 29,544 29,544 29,544 29,544
Useful MEMS wafer area for 200 mm
wafer [AreaM200]
mm
2
AreaM200 = pi
∗
(D/2 – MWE)ˆ2 25,434 25,434 25,434 25,434 25,434
CMOS circuit area incl. outside bond pads
[CA]
mm
2
Input CA 0.5 1 2 3 4
MEMS area [MA] mm
2
Input MA 0.5 0.5 0.5 0.5 0.5
MEMS chip bond pads area [MBA] mm
2
Input MBA 0.05 0.05 0.05 0.05 0.05
Yield MEMS [YM] % Input YM 90.0% 90.0% 90.0% 90.0% 90.0%
Yield packaging and test [YPT] % Input YPT 96.0% 96.0% 96.0% 96.0% 96.0%
Yield CMOS (area dependent!) [YCMOS] % YCMOS = 1–(CA
∗
0.005) 99.8% 99.5% 99.0% 98.5% 98.0%
Yield Integrated MEMS [YieldIM] % YieldIM =
YM
∗
YCMOS
∗
0.85
1
76.3% 76.1% 75.7% 75.4% 75.0%
Good CMOS chips per 200 mm wafer
[NumC200]
# NumC200 = (AreaC200/CA)
∗
YCMOS
58,941 29,397 14,624 9700 7238
Good MEMS chips per 200 mm wafer
[NumM200]
# NumM200 = [AreaM200/(MA +
MBA)]
∗
YM
41,619 41,619 41,619 41,619 41,619
Good integrated chips per 200 mm wafer
[NumIM200]
# NumIM200 = [AreaM200/(CA +
MA)]
∗
YieldIM
19,408 12,906 7705 5476 4237
a
Using a MEMS-only, a CMOS-only, and an integrated MEMS (i.e., MEMS integrated with CMOS on the same substrate) process technology
b
We have assumed that when MEMS is integrated with CMOS that the collective yield will be the product of the yields of each of the process technologies
and the resultant yield of the integration process, which is taken as 85% in the present example
1170 M.A. Huff et al.
The one set of entries in Tables 14.3 and 14.4 that are highly process-dependent
(and also dependent on the die area) is yield. In general, there are standardized
models for estimating yield for integrated circuits based on the number of defects
per unit area and the die area [100, 101]. In general, similar statistical techniques
can be used for MEMS production. It is important to note that the yield for a process
technology always decreases as the die size increases. Having a yield that decreases
with increasing die size is typical for semiconductor production because the proba-
bility of a random particulate or defect causing a device failure increases as the die
gets larger.
In order to estimate the yield, the number of defects per unit area must be known,
which will not be the case unless the process technology is already in produc-
tion. In Tables 14.3 and 14.4 we show the MEMS die yield (i.e., yield for wafers
having only MEMS devices without CMOS on the same substrate) as 90% and
constant, inasmuch as in this model the MEMS die size is constant. As calculated
for the CMOS die, the die size does vary and therefore the yield is dependent on
the area of the die, which for the present example is calculated according to the
equation Yield CMOS = YCMOS = 1 – (die area [mm]
2 ∗
0.005). (Note that
this would translate into a yield of 99.5% for a die that is 1 mm
2
.) In addition,
there is another yield entry after packaging and testing of 96% that corresponds
to the number of devices that meet the acceptance criteria after packaging and
testing.
In our example, this is assumed to be independent of whether the packaging is for
a hybrid approach or for an i ntegrated MEMS device. The yield of package and test-
ing of CMOS is usually very high, therefore we have assumed it to be 100% in our
example. Lastly, the yield of the integrated MEMS, wherein the MEMS and CMOS
are fabricated on the s ame wafer in this example is calculated by taking the product
of the MEMS die yield, the CMOS die yield, and a factor for the yield for integrat-
ing these two processes on the same substrate, which is assumed to be 85% in this
example. In the case of the first data column of Table 14.3, the yield for integrated
MEMS, 76.3%, is calculated from 90%
∗
99.8%
∗
85%, and the good integrated
chips per 150 mm diameter wafer are equal to (13,267/(0.5 + 0.5))
∗
76.3%, or
10,124. This represents that increasing the number of photolithographic steps and
combining MEMS and microelectronics on the same substrate will typically reduce
the yield.
The last three rows of Tables 14.3 and 14.4 calculate the number of good die
for the three cases of CMOS-only die, MEMS-only die, and MEMS-integrated with
CMOS die for both 150 and 200 mm diameter wafers, respectively. Essentially these
calculations take the usable area of the wafer and divide by the die area and then
multiply by the yield. For the case of the MEMS-only die, the total die area is
the sum of the MEMS area and the MEMS chip bond area. The number of good
integrated MEMS die is calculated by summing the area of the CMOS and MEMS
die, but neglecting the MEMS chip bond area because no MEMS device-specific
bond pads are needed in the case of the MEMS integrated with CMOS.
Now that the number of die has been determined, we can calculate the cost
of the die. Tables 14.5 and 14.6 calculate the cost per die for the three process
14 MEMS Process Integration 1171
Table 14.5 Calculation of the cost per die for a MEMS-only, CMOS-only, and integrated MEMS
a
Cost calculations
Additional mounting cost for 2 chips
[AM Cost]
$ Input AM Cost 0.04 0.04 0.04 0.04 0.04
Packaging and test cost [PT C ost] $ Input PT Cost 0.12 0.12 0.12 0.12 0.12
CMOS wafer cost 150 mm Asia for 2 chip
[CWCost150]
$ Input CWCost150 600 600 600 600 600
CMOS wafer cost 150 mm for integration
[ICWCost150]
$ Input ICWCost150 700 700 700 700 700
MEMS wafer cost 150 mm [MWCost150] $ Input MWCost150 800 800 800 800 800
Discrete CMOS chip cost 150 mm (0.35 µm)
[DCCC150]
$ DCCC150 =
CWCost150/NumC150
0.018 0.037 0.074 0.112 0.150
Integrated chip cost 150 mm [ICC150] $ ICC150 = (ICWCost150 +
MWCost150)/NumIM150
0.148 0.223 0.373 0.525 0.679
Discrete MEMS chip cost 150 mm
[DMCC150]
$ DMCC150 =
MWCost150/NumM150
0.037 0.037 0.037 0.037 0.037
a
MEMS integrated with CMOS on the same substrate) process technology on 150 mm diameter wafers. As in Tables 14.3 and 14.4, the columns represent
CMOS controller die areas of 0.5, 1, 2, 3, and 4 mm
2
, respectively
1172 M.A. Huff et al.
Table 14.6 Calculation of the cost per die for a MEMS-only, CMOS-only and integrated MEMS
a
Cost calculations
Additional mounting cost for 2 chips
[AMCost]
$ Input AM Cost 0.04 0.04 0.04 0.04 0.04
Packaging and test cost [PT C ost] $ Input PT Cost 0.12 0.12 0.12 0.12 0.12
CMOS wafer cost 200 mm Asia for 2 chip
(0.18 µm) [CWCost200]
$ Input CWCost200 800 800 800 800 800
CMOS wafer cost 200 mm for integration
(0.18 µm) [ICWCost200]
$ Input ICWCost200 900 900 900 900 900
MEMS wafer cost 200 mm [MWCost200] $ Input MWCost200 1000 1000 1000 1000 1000
Discrete CMOS chip cost 200 mm (0.18 µm)
[DCCC200]
$ DCCC200 =
CWCost200/NumC200
0.014 0.027 0.055 0.082 0.111
Integrated chip cost 200 mm [ICC200] $ ICC200 = (ICWCost200 +
MWCost200)/NumIM200
0.098 0.147 0.247 0.347 0.448
Discrete MEMS chip cost 200 mm
[DMCC200]
$ DMCC200 =
MWCost200/NumM200
0.024 0.024 0.024 0.024 0.024
a
MEMS integrated with CMOS on the same substrate, process technology on 200 mm diameter wafers. As in Tables 14.3 and 14.4, the columns represent
CMOS controller die areas of 0.5, 1, 2, 3, and 4 mm
2
, respectively
14 MEMS Process Integration 1173
scenarios for both a 150 mm diameter wafer (Table 14.5) and a 200 mm diame-
ter wafer (Table 14.6). The costs per die are calculated by taking the input values
of wafer processing costs for each of the scenarios (these input fields are shaded)
and dividing by the number of good die from each process type and wafer diameter
from Tables 14.3 and 14.4. Two types of CMOS processes are shown, specifically
a 180 nm process technology on 150 mm diameter wafers and a 350 nm process
technology on 150 mm diameter wafers. The production cost per wafer for a CMOS
process is based on commercial rates, however, the same is not true for the MEMS
wafer processing costs, which can vary from one MEMS process technology to
another. For simplicity, we have assumed a mature MEMS wafer process technol-
ogy with a cost of $800 and $1000 per wafer on 150 and 200 mm diameter wafers,
respectively, as shown in Tables 14.5 and 14.6. Using the number of good die for a
150 mm diameter wafer in Table 14.3, we calculate the cost per die for a 150 mm
diameter wafer as shown in Table 14.5. Likewise, the number of good die for a
200 mm diameter wafer from Table 14.4 can be used to calculate the cost per die for
a 200 mm diameter wafer as shown in Table 14.6.
These conceptual cost models are based on the production of a straightforward
surface-micromachined MEMS device. In the integrated case, the MEMS process
technology is mixed with a circuit process technology such that a single die con-
tains both the MEMS device and microelectronics. In the nonintegrated case, the
MEMS device, with no circuitry, is on one chip and the circuitry is fabricated on a
standard commercially available CMOS process technology. Both devices are pack-
aged, assembled, and tested using the same methods and equipment. In all other
respects, the integrated and nonintegrated MEMS devices are equivalent.
The first and most obvious difference is the cost of the MEMS device wafer.
In the integrated process case, the cost represents a very sophisticated, complex,
and high mask count process technology. The process complexity requires a large
amount of fabrication infrastructure that must be amortized. The yield, although
high, is reduced because of this complexity. The nonintegrated MEMS device is
a much simpler and lower mask count process technology and the wafer cost is
correspondingly lower. On the other hand, the nonintegrated process technology
requires an ASIC wafer. However, because it can be produced in a s tandard com-
mercial CMOS process technology, it can take advantage of the full economies
of scale (not to mention the ever-increasing circuit density) of such a process
technology.
The backend processes for both cases are very similar. Because of the complex-
ity of the integrated MEMS process technology, 100% testing is almost always
appropriate. In the nonintegrated process technology, 100% testing of the MEMS
device is also generally recommended due to the large process variations associ-
ated with MEMS manufacturing. Testing of a standard commercial CMOS wafer,
on the other hand, is often not cost effective. In this case, it is assumed that the
ASIC wafer is not tested. Although the testing costs of the integrated and noninte-
grated devices are shown as equivalent, it is often the case that the cost of testing
the MEMS-only wafer is higher than the integrated wafer, due to the added time and