Ghodssi R., Lin P., MEMS Materials and Processes Handbook

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1154 M.A. Huff et al.

Silicon Substrate

Vias

MOS

Metal 1

Metal 2

Metal 3

Metal 4

Polysilicon

(a). Cross section of substrate received from CMOS

foundry (4-layer metal process technology).

(b). CMOS substrate is mounted upside down on a handle

substrate and photolithography is performed to open up

regions on the backside of the CMOS silicon substrate.

Silicon Substrate

Handle Substrate

(c). The exposed silicon on the backside of the CMOS

substrate is then etched using DRIE.

Handle Substrate

(d). The CMOS substrate is then etched using an isotropic

silicon etchant to undercut the silicon as shown.

(e). RIE is performed on the CMOS substrate frontside

through the dielectric layer stack and stopping on the

silicon substrate.

(f). DRIE is performed on the CMOS substrate frontside

through the silicon substrate.

(g). Optional timed isotropic silicon etch to remove silicon

under certain regions.

Silicon Oxide

CMOS

Metal

Polysilicon

Fig. 14.87 Process sequence for ASIM-X process

and a photolithography step is performed on the top surface of the substrate. The

exposed regions of the multiple-layer dielectric on the CMOS substrates are then

etched using a RIE and stopping on the silicon substrate (Fig. 14.87e). Without per-

forming additional photolithography, a DRIE is performed on the substrate front

side (Fig. 14.87f). Optionally, an isotropic silicon etch may be performed to under-

cut the narrow beams made in the silicon etch process to create released structures

of the multilayer CMOS metallization stack without silicon beams underneath

(Fig. 14.87g). A derivative of the ASIMPS process is used by Akustica for the

production of commercial microphones.

14.8.3.7 Integrated CMOS+RF MEMS Process (wiSpry)

A large number of RF MEMS processes have been developed over the last 10–15

years. In general, each of these processes has been developed to construct a speciﬁc

RF MEMS device, such as a series switch, capacitive switch, variable capacitor,

inductor, and so on [89–91]. Few of these processes have demonstrated the ﬂexibil-

ity to produce the range of devices that would support a full RF subsystem, such as

a phase shifter or tunable ﬁlter.

The materials required for RF MEMS have more speciﬁc requirements than are

required for quasi-static electromechanical MEMS. Insulators require low dielec-

tric constants and low loss-tangents. Depending on the application they can also

14 MEMS Process Integration 1155

require high breakdown ﬁelds. Conductors i n general require higher bulk conduc-

tivities than would be acceptable for a quasi-static application. In the case of contact

switches, the contacting conductor’s properties are critically important to both the

electrical performance and the lifetime. A great deal of work has been done to try to

understand the contact switching behavior of various MEMS metals and alloys [92].

Contact resistance as a function of contact force and contact wear characteristics

must be well characterized and understood to provide a reliable high-performance

device.

WiSpry, a start-up RF MEMS company, set out to develop a process that was

ﬂexible enough to support a full range of RF MEMS devices [93]. They focused

on low deposition temperature CMOS-compatible processing steps with low stress

and low loss materials. They chose silicon dioxide as the MEMS structural layer for

its good mechanical properties and its ability to electrically isolate the signal and

actuation areas within a device. They chose thick copper as the via and interconnect

conductor to provide high conductivity and process compatibility. They chose thin

gold as the surface electrode and switch contact conductor because of its low contact

force and subsequent low contact resistance, and low self-adhesion leading to good

contact wear performance.

The WiSpry process is a “CMOS ﬁrst” process that starts with a commercial

0.18 µm HV CMOS process on a low-resistivity 200 mm silicon wafer. The MEMS

process is divided into three sections: substrate connect, thick metal, and thin metal.

The substrate connect process uses the standard CMOS metallization to route and

connect to vias that connect up to the ﬁrst thick metal layer.

The thick metal section is constructed by depositing 3.5 µm of copper embedded

in silica and planarized with CMP. Then another 3.5 µm layer of copper is deposited

and planarized to form stud interconnect (vias). Figure 14.88 shows a process cross-

section that contains one of these 7 µm thick double metal layers; however, this

MEMS Lid

MEMS Beam

MEMS Metal

CMOS Metal

HV CMOS

Fig. 14.88 Cross-sectional diagram showing the layers of the WiSpry CMOS ﬁrst integrated RF

MEMS process: CMOS and its interconnect layers (HV CMOS and CMOS Metal), thick metal

interconnect layer (MEMS Metal), the gold counterelectrode layer, the gold metallized silicon

dioxide structural layer (MEMS Beam), and the wafer-level cap (MEMS Lid) (Reprinted with

permission, copyright WiSpry, Inc.)

1156 M.A. Huff et al.

double deposition can be repeated multiple times. The nominal process uses two of

these layers.

The thin metal section forms the surface electrodes, switch contact surfaces, and

released MEMS structures. It is composed of three layers of 0.5 µm thick gold, one

deposited on the insulating surface of the underlying thick metal section, and one on

the upper and lower surface of the released MEMS “beam.” The sacriﬁcial layers

that allow construction and then release of the silica beam are a 1.5 µm copper layer

(below) and a 0.5 µm copper layer (above).

The MEMS structure is encapsulated at the wafer level to protect the MEMS

device from contamination, moisture, and the backend processing, such as ﬂip-chip

processing, back grinding, dicing, and assembly. Figure 14.89 shows a cross-section

of the entire structure. This integrated MEMS+CMOS die is then ﬂip-chip mounted

to a substrate to provide a ﬁnal product solution.

MEMS Lid

MEMS Beam

MEMS Metal

CMOS Metal

HV CMOS

Fig. 14.89 Cross-section showing the CMOS Metal layers, the copper interconnect layer (MEMS

Metal), the gold counterelectrodes, the MEMS beam and the wafer-level cap (MEMS Lid)

(Reprinted with permission, copyright WiSpry, Inc.)

14.8.3.8 Integrated SiGe MEMS (UCB)

The SiGe process module is intended to solve the problem of merging crystalline

semiconductor materials with electronics [94–96]. As a general rule, a CMOS wafer

with metallization and transistor device junctions cannot be exposed to temperatures

above about 450

◦

C without degradation of the microelectronics, thereby placing

severe restrictions on the types of processing steps which can be employed for a

“MEMS last” monolithic integration strategy. Typically, crystalline semiconduc-

tor materials, such as polycrystalline silicon or polysilicon, are deposited using

LPCVD due to its inherently low cost and simple processing, as well as the high

quality ﬁlms that are produced with this technology. However, the deposition tem-

peratures of LPCVD polysilicon are well above 450

◦

C (they are typically in excess

of 600

◦

C). Furthermore, it is almost always necessary to anneal LPCVD deposited

polysilicon ﬁlms at temperatures above 900

◦

C to reduce the residual stress and stress

gradient for the material to be useful as a structural micromechanical layer for the

implementation of MEMS devices.

14 MEMS Process Integration 1157

One approach to avoiding this problem is to fabricate the MEMS ﬁrst and then

proceed to the fabrication of the CMOS. An example of this is the Sandia Integrated

MEMS process technology, which is reviewed in the next section [97]. Another

strategy is the MEMS last wherein the MEMS are made from a completed CMOS

wafer using the silicon substrate and thin-ﬁlm layers from the CMOS process to

implement the MEMS devices. Both of these approaches have their respective

advantages and disadvantages [94–97].

Another example of a MEMS last approach was recently reported by UCB [95,

96] and uses LPCVD polycrystalline silicon germanium (SiGe) as the structural

micromechanical material layer rather than polycrystalline silicon (polysilicon). The

advantage is that SiGe can be deposited at a much lower temperature than polysil-

icon, thereby allowing CMOS wafers from virtually any foundry to be used in this

process to obtain monolithically integrated MEMS–CMOS.

The sequence is essentially a surface micromachining MEMS process

(Fig. 14.90). The f ully metallized and completed CMOS wafer has photolithog-

raphy and etching performed to open up vias to the underlying polysilicon lines

in order to make electrical connection from the MEMS to the CMOS microelec-

tronics. It is possible to open up vias to the metal, but this risks contaminating the

SiGe deposition process tool with a metal and therefore the CMOS polysi is used

as the electrical interconnection layer. A LPCVD deposition of Si

0.35

0.65

is per-

formed at 450

◦

C that is approximately 400 nm in thickness. This layer will act as

Silicon Wafer

P Well

Germanium

SiO

polysilicon

P Well

Via

(a)

Starting CMOS wafer with via etched through

silicon dioxide on surface to make contact to

polysilicon layer.

(b) Deposition and patterning of

Silicon Germanium layer.

(c)

Wafer after deposition and patterning of

Germanium layer and second p+ Silicon

Germanium layer.

(d)

Wafer after release whereby Germanium

layer is removed by immersion in hydrogen

peroxide.

Silicon GermaniumPolysiliconSilicon Dioxide Metal

Silicon Germanium

SiGe

Silicon Germanium

Fig. 14.90 Process sequence for UCB silicon germanium monolithically integrated CMOS–

MEMS process technology

1158 M.A. Huff et al.

a ground plane for the MEMS devices. The layer is deﬁned using photolithogra-

phy and RIE etching. Next, a pure germanium layer is deposited at 375

◦

C, which is

2 µm in thickness and will act as a sacriﬁcial layer in this surface micromachining

process.

A two-step photolithography can now be performed on the sacriﬁcial layer: the

ﬁrst to make shallow dimples to reduce stiction effects and the second to open up

anchors and electrical connections from the structural layer to the ground-plane.

Given the low selectivity of the germanium RIE etch compared to the underlying

0.35

0.65

layer, a very thin layer of LTO is used between these two layers as an

etch stop. After the LTO is removed in the anchor regions using short-duration HF

immersion, a structural layer of Si

0.35

0.65

is deposited by LPCVD at 450

◦

Cto

a thickness of 2.5 µm. This structural layer is then deﬁned using photolithography

and RIE etching. The MEMS device is then released by immersion of the substrate

into a solution of hydrogen peroxide (H

), which is safe to use with the CMOS

devices.

Although this process is very simple compared to many of the other monolithic

integration approaches, a major disadvantage is the length of time that the wafers are

held at 450

◦

C for the poly SiGe depositions, which is over 3 h. Consequently, this

process is appropriate for use with older CMOS technologies wherein the diffusion

depths and metal linewidths are not too aggressive. To overcome this limitation, sev-

eral groups have been working to develop a technology to deposit poly SiGe using

PECVD or a combination of PECVD and LPCVD with the purpose of reducing the

time the wafers are held at higher temperatures as well as opening the capability of

depositing thicker structural layers.

14.8.3.9 Integrated SUMMiT (Sandia)

The Integrated Summit process was developed by Sandia National Labs in the early

to mid-1990s and is a sophisticated process technology that monolithically inte-

grates MEMS surface-micromachined components with CMOS microelectronics

[97]. This integrated MEMS process technology is termed a so-called “MEMS ﬁrst”

process whereby the MEMS components are fabricated on the wafers ﬁrst and then

the wafers are processed through a standardized CMOS process line to fabricate the

microelectronics. The Sandia approach of using MEMS ﬁrst was to create a deep

trench in the surface of the wafer within which the MEMS devices are then fabri-

cated, followed by chemical mechanical polishing to planarize the wafer surfaces so

that they can be processed on a CMOS fabrication line.

This approach provides two major processing advantages compared to either an

“interleaved MEMS” process technology (such as the Analog Devices’ iMEMS

process described above) or a MEMS last process technology (such as the CMU

ASIMPS process described above). Speciﬁcally, the MEMS ﬁrst approach devel-

oped by Sandia eliminates the large topology on the substrate surface because

the MEMS are embedded into the substrate, which is then planarized so that it

can be processed on a CMOS process equipment set. Secondly, inasmuch as no

microelectronics fabrication begins until the MEMS are made, there is a very

14 MEMS Process Integration 1159

high thermal budget available for the MEMS fabrication. Therefore, the materi-

als used in the MEMS fabrication, such as polycrystalline silicon can be deposited

at higher temperatures and therefore higher rates, and these materials can be

annealed at temperatures sufﬁcient to relieve the residual stress in the as-deposited

layers.

Although this process solves some major technical challenges of integration of

MEMS with microelectronics, it also presents a potentially major disadvantage as

well. This process technology was developed by a government laboratory, which had

both very advanced MEMS and CMOS fabrication capability. To be of maximum

beneﬁt to the community, the MEMS ﬁrst processing and the CMOS last process-

ing could be performed at different foundries. This would allow much broader use,

market acceptance, and penetration. However, a major question with this process is

whether a CMOS foundry would allow preprocessed wafers with MEMS devices

embedded into the substrates to be processed on their process line.

The Sandia Integrated MEMS process technology begins with standard silicon

wafers (Fig. 14.91). A photolithography step and etching is performed on the sub-

strate surface to create alignment marks that will be used in subsequent processing

(a) Starting wafer with 6 micron deep trench

etched into surface.

Water after SiN deposition and patterning

in trench region.

Wafer after multiple layers of polysilicon and

oxide have been deposited and patterned to form

the bottom electrode, the MEMS structural layer

and the surrounding sacrificial layer.

(c)

(d) Wafer after deposition and patterning of SiN

capping layer where MEMS are located.

(e) Wafer after fabrication of CMOS in field regions

and followed by the deposition and patterning o

a SiN layer over the CMOS to protect the

electronics during the release process.

(f) Wafer after release of the MEMS devices by

removal of the sacrificial oxide in the trench

areas.

Trench

Silicon Wafer

Silicon Wafer Silicon Wafer

Silicon Wafer

Silicon Nitride

Unreleased Micromachined

Structures

Contact Stud

Silicon Nitride Capping Layer

Sacrificial Layers

CMOS

Interconnection Metal of CMOS

Silicon Silicon Nitride Polysilicon Silicon Dioxide Metal

(b)

Fig. 14.91 Process sequence for Sandia’s Integrated MEMS process

1160 M.A. Huff et al.

steps. Next, another photolithography is performed, followed by a KOH anisotropic

wet chemical etch to form a trench that is approximately 6 µm deep into the top

surface of the wafer. The sloping sidewalls of the resultant trenches are used as an

advantage in this process sequence. They improve the photolithography processes

used to deﬁne the MEMS structures, which are made at the base of the trench. That

is, depositing photoresist onto the surfaces at the bottom of the trench would be

more difﬁcult if the edges of the trenches were vertical. Normally there would be

a disadvantage with these sloping trench sidewalls as well, namely the ability to

resolve ﬁne features for the MEMS structures in the trenches due to the separation

between the mask and the layer to be patterned. However, Sandia claims that by

making alignment marks at the bottom of the trenches, the resolution of the MEMS

features can be improved to about 1 µm. Nevertheless, this does add an additional

photolithographic step to the overall process ﬂow.

A silicon nitride layer is next deposited using LPCVD on the wafer to create

a dielectric layer on the bottom of the trenches. This layer is deﬁned using pho-

tolithography and a RIE etch. Next, a layer of polycrystalline silicon is deposited

using LPCVD and then this layer is deﬁned to make the bottom electrodes for the

MEMS devices using photolithography and etching. A s ilicon dioxide (SiO

) layer

is deposited using LPCVD which will act as the sacriﬁcial layer for the MEMS

device processing. This oxide layer is deﬁned using photolithography and etching.

Another polycrystalline silicon layer is deposited using LPCVD and this layer is

deﬁned to make the structural mechanical layer for the MEMS devices using pho-

tolithography and etching. The depth of the trench must be accurately controlled so

that the contact stud can be formed to make electrical contact between the micro-

electronic interconnect metal layer and the MEMS structural layer. Subsequently,

the trench is ﬁlled with a deposited oxide using a deposition technique that does not

result in any voids.

The surface of the MEMS-processed wafer is then planarized using CMP result-

ing in a surface topology essentially equivalent to that of a prime silicon wafer.

The wafer is also annealed at a high temperature to relieve any residual stresses

in the micromechanical material layers, speciﬁcally the polysilicon structural layer.

A layer of silicon nitride is then deposited onto the wafer and deﬁned using pho-

tolithography and etching to result in a capping layer of SiN over the areas of the

wafer where the MEMS structures are located, and the SiN is removed where the

CMOS is to be fabricated.

The wafer is then ready for the CMOS fabrication wherein the microelectron-

ics are fabricated in the substrate ﬁeld regions (i.e., the s ubstrate surface areas

where the MEMS structures are not located) using a standard CMOS process ﬂow.

A metal interconnection layer runs from the CMOS to the contact stud previously

fabricated in the area of the wafer where the MEMS are located to make electrical

connection between the CMOS and MEMS. At t he completion of the CMOS pro-

cess sequence, the capping layer of SiN is removed so that the MEMS structures

can be released using a HF immersion to remove the oxide material surround-

ing the MEMS structural polysilicon layer. The CMOS is protected by a layer of

photoresist.

14 MEMS Process Integration 1161

The Sandia Integrated MEMS process technology is highly modular, wherein

the MEMS fabrication is distinct from the CMOS fabrication and vice versa,

thereby potentially allowing this technology to be implemented with a num-

ber of CMOS process technologies available from any number of commercial

foundries. However, as mentioned above, many commercial CMOS foundries

may be reluctant to use preprocessed wafers with embedded MEMS structures

in their CMOS fabrication lines. Other disadvantages of this process technology

include: the photolithography of the MEMS structures performed at the bottom

of the trenches limits the linewidth resolution of the MEMS structures; this pro-

cess technology has a large number of processing steps including photolithography

processes; it is important that high-quality deposited oxides are used for the sac-

riﬁcial oxide layers to avoid voids and out-gasing during subsequent processing

steps; and the thickness of the MEMS structural layer is limited to only a few

microns.

14.9 The Economic Realities of MEMS Process Development

The amount of investment required to develop and manufacture a MEMS device has

a huge impact on whether a MEMS business venture will be successful. The amount

of time it takes to develop a MEMS device is also extremely important for many

new technology-based products due to the limited window of market opportunity.

The purpose of this section is to convey some guidance about the cost and time

involved in MEMS development and as part of that discussion we demonstrate some

of the techniques often used to estimate the cost of MEMS devices before they are

in production. Ultimately, business ventures are most concerned about the return

on investment (ROI). Ideally, a MEMS business venture would want to be able to

estimate these costs and schedules as accurately as possible before any signiﬁcant

funds have been spent on development, so that the ROI can be predicted at the

outset.

14.9.1 Cost and Time for MEMS Development

By now the reader will know that MEMS development can be a very challenging

endeavor, but the question we now address is how much time and money can be

expected to be spent on developing a new MEMS device. For example, unless the

MEMS developer is fortunate enough to be able to access an existing (i.e., already

fully developed) process technology, he or she will inevitably be required to develop

a process sequence. Obviously, this will have a huge impact on the product’s ROI.

Given the truly enormous range of MEMS devices, applications, and methods used

for implementation, it should not be surprising that there is no single formula for

making these estimations. Indeed, as with much else related to MEMS technology,

these kinds of analyses require access to a signiﬁcant amount of information and

1162 M.A. Huff et al.

considerable practical experience to do them well. Nevertheless, we review some

basics of how these estimations are performed in order to give the reader some

appreciation of the factors and issues involved.

First, it is important to set some ground rules as to what is included in the estima-

tion of development costs for a MEMS device. Speciﬁcally, there are many possible

items that may be included, such as: setting up a foundry facility, setting up a pack-

aging facility (which may or may not be considered part of the foundry facility),

procurement of fabrication equipment capital tooling, procurement of packaging

equipment capital tooling, procurement of testing equipment capital tooling, tech-

nology licensing fees, and so on. These cost items can vary over a very large range

of values depending on many factors including the scale of the operation, the type

and automation level of the facility and tools, and whether any development may be

required for these resources.

It would be wrong to assume that all the required fabrication equipment, facil-

ities, packaging, and testing equipment for the production of a MEMS device will

be readily available from equipment suppliers. For example, many of the companies

who entered into the MEMS inertial crash airbag sensor market found that pro-

duction testing equipment for inertial sensors was not available from any supplier

and therefore they were forced to develop this capability themselves at signiﬁcant

expenditure of both time and money. This is a relatively frequent occurrence for

many companies who are going into new application areas of MEMS technology.

Obviously, such a situation can have a big impact on the development cost and

schedule. The determination of whether the needed production equipment resources

are available by procurement is best determined by a careful review by experienced

MEMS fabricators.

In estimating the total cost to produce a MEMS product it is common practice

to break the total cost into two elements: the nonrecurring expenses and the recur-

ring expenses. Nonrecurring expenses are ﬁxed costs and are mostly independent

of sales volume. They include the expenses involved in developing a new product

design that is manufacturable. Recurring expenses are variable costs and depend on

the sales volume. They account for the costs directly attributable to manufacturing

the product and typically include material costs, fabrication costs, assembly costs,

testing costs, and the like.

The nonrecurring or ﬁxed expenses are examined ﬁrst. For the ﬁxed expenses,

we separate the costs to build the manufacturing capability, including the cost of the

capital tooling, from the actual costs of device development, what are commonly

termed the nonrecurring engineering (NRE) costs. It s hould be noted that there is

a coupling between the development cost, the existence of (or lack of) accessible

foundry infrastructure, and the mode of access to these resources, but for the sake of

simplicity, we ignore these effects in this discussion and review foundry costs ﬁrst.

There are relatively well-developed methods for estimating the costs of estab-

lishing integrated circuit foundries based on the size and number of substrates to

be produced on an annual basis and the type of process technology that will be

employed in production (e.g., 45 nm CMOS, DRAM, etc.). For example, the cost

to build and equip a state-of-the-art 300 mm integrated circuit foundry has reached

14 MEMS Process Integration 1163

several billion dollars. The cost of integrated circuit foundries has exponentially

increased over the past few decades from around $10 million in the early 1970s to

over $3 billion today and this cost escalation is expected to continue in the future.

What is surprising, however, is that the per-unit cost of the die produced in these

facilities has continued to drop despite the large increase in foundry costs. The

major reason for this is the fact that larger foundries can produce more ICs. These

foundries have equipment to process larger wafers, which enables more die real

estate to the square power.

The smaller linewidths that can be produced in these state-of-the-art foundries

allow the die to be made smaller, allowing more die per wafer. These attributes

allow the cost to be driven out of the production at a rate faster than the rate

at which foundry costs are increasing. It is important to note that the output of

modern integrated circuit foundries has reached such high production levels that

many companies cannot utilize the entire production capacity that these facil-

ities are capable of manufacturing for their internal needs. This coupled with

the requirement of very high capacity utilization levels in order to cover the

enormous costs of building and operating these foundries has resulted in the

increasingly common practice of many companies to outsource the manufactur-

ing of integrated circuits. As a consequence, the number of companies retaining

integrated circuit production core competencies is decreasing every year, with

more and more production capability being pooled into very large pure-play

foundry operations, such as Taiwan Semiconductor Manufacturing Corporation

(TSMC).

The foundry situation for MEMS is quite different. The estimation of the costs

of establishing the required f oundry facility infrastructure for a MEMS technology

can vary over a huge range, with commensurately large variations in the cost of

procuring and installing the required fabrication process equipment. Speciﬁcally,

the cost of building and facilitating a dedicated MEMS foundry (i.e., no integrated

circuit manufacturing capability) including capital equipment tools may range from

a few $10 s of millions on the low side to a few $100 s of millions or more on the

high side. The range is largely determined by the size of the foundry, the size of the

substrates being processed, the number of tools required, and the level of automation

of these tools. In addition, the time it can take to build a foundry and procure and

install the processing equipment is between one to 2 years or more and therefore

must be considered in the development schedule (integrated circuit facilities take a

similar amount of time to build and equip).

The primary reason that MEMS manufacturing facility costs are far lower than

integrated circuit f oundries is that most MEMS process technologies do not push the

technology envelope of nanometer scale linewidth resolutions (a minimum resolu-

tion of a few microns is usually acceptable in a MEMS process technology), larger

wafer sizes are not needed or even desired (because the required maximum produc-

tion volumes are much lower, MEMS foundries are typically at the 150 mm wafer

diameter level, whereas IC foundries process 300 mm wafers), and high levels of

automation are not required or desired (automation often results in broken MEMS

wafers!). Consequently, it is common to see many MEMS foundries reconﬁgured