Ghodssi R., Lin P., MEMS Materials and Processes Handbook
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1064 M.A. Huff et al.
luck). The technologies employed as well as the people involved must all be care-
fully selected and may vary considerably in specific skill sets from one type of
development project to another. A successful effort requires t he fortitude to over-
come the constant stream of problems and disappointments that often occur on any
MEMS development effort. This requires experienced technologists led by people
with both strong leadership skills and technical understanding, who can direct the
team to focus on the most practical and timely solutions to these problems. It is
important that the process designers and developers be brought into the develop-
ment effort very early (e.g., day one) and work closely with the device and product
designers t o provide their guidance on the implementation of the device and product.
It is also important that the decision makers for the process approaches be “process
agnostics.”
It would be incorrect to assume that there is a one-size fits all, fool-proof, or
even “well-proven and demonstrated” strategy or set of principles for successfully
developing a MEMS process sequence. The s kills for successful process develop-
ment include: very creative instincts, an encyclopedic knowledge of what has been
demonstrated in the art, a high level of intuition, good device design capability, the
ability to correlate facts from different domains, the ability to handle multivariable
spaces with ease, and years or decades of hands-on experience. In short, these are
not skills that can be easily conveyed or taught in one book, let alone one chapter
of a book. It should be understood that even for the most gifted (or lucky) process
developer, MEMS process development entails a considerable amount of iteration
and perfecting, based on the ability to quickly learn from previous experiments (i.e.,
mistakes), and developing strategies for advancing the process development to a
successful conclusion.
Figure 14.8 is a simple high-level illustration of the general approach taken for
developing a MEMS process sequence. In the first phase, the Conceptual Phase, the
device design and process sequence for implementing the design are created. This
work will involve several stakeholders including device designers and fabrication
Fig. 14.8 The strategy for MEMS process development (Reprinted with permission, copyright
MEMS and Nanotechnology Exchange)
14 MEMS Process Integration 1065
experts as well as business and marketing people. Many compromises will be dis-
cussed and made by these stakeholders in order to obtain an outcome that will be
thought to meet the performance, cost, and time-to-market goals. It is often prudent
to have several potential approaches for the implementation of the MEMS device at
the conclusion of this stage. It is important to note that the design models, whether
analytical or numerical, are not likely to be based on accurate values for the material
properties because these are process dependent (see discussion above). Therefore,
the designers will need to make reasonable estimates of these values in their design,
with the goal of “bounding the problem.” The output of the designer’s efforts will be
a set of models, a preliminary process sequence(s), and a prototype mask layout set.
Similarly, the fabrication experts will not be able to predict the outcome of either
the process sequence(s) or even each processing step with certainty, but will use their
experience and judgment to point out the individual processing steps and portions
of the processing sequence(s) that will need the most development work and have
the highest risk. The fabricators will formulate a strategy, based on the principles
of design of experiments (DOE) to develop the individual processing steps that will
need to be generated. They will design short-loop runs (i.e., subsets of steps) also
based on statistical methods such as DOE to develop portions of the process (i.e.,
process modules) as well as the entire sequence. In addition, they will work with
the designers to create the designs for a set of test structures that will be useful for
measuring the properties of the materials used i n the process sequence as well as
diagnostic structures and devices to help with the process development. The output
from the fabrication experts at this stage will be a set of DOEs for all process steps
and short loop process runs for the sequences.
With the designs in hand, along with a set of planned process experiments, the
work in the fabrication laboratory begins to develop the processing steps, modules,
and ultimately the sequence. Much of this work is iterative at many levels. The
development of process steps varies the processing parameters over a set of reason-
able values, followed by measurement of the outcomes, which are then documented
and statistically analyzed. Similarly the efforts to develop modules and sequences
will rely on the outcome of a number of short loop experiments, which will also be
documented and statistically analyzed. The benefit of well-thought-out, statistically
significant experiments for such work cannot be overemphasized!
Once parts of the process sequence are beginning to mature, test structures will
be fabricated and measurements taken to determine accurate dimensions and the
material property values. These values will be fed back into the design models and
new models will be created. Once the process sequence starts to come together and
working devices are beginning to be yielded from the runs, the design and mod-
els are further refined, new mask sets are created and the iterations continue. It is
reasonable to expect that the first two or more cycles of a new and customized pro-
cess sequence may not initially yield any working devices. It is also reasonable to
expect that once working devices are beginning to be yielded on the runs, that the
yields will be below 25%, although higher yields are possible. During subsequent
process runs, various quality improvement methods (e.g., pareto, histograms, etc.)
can be employed to increase the yield to above 50%. At some point, the process
1066 M.A. Huff et al.
of volume learning begins whereby a large enough volume of wafers has been run
that the small yield-killers can be reduced or eliminated. Obviously, the cost and
development time are heavily influenced by the complexity of the process sequence
for any device type. It is not uncommon to see very large development costs (e.g.,
in excess of $100 M) for complex MEMS process technologies, such as integrated
MEMS devices.
14.6.1 Integrated MEMS Process Integration Strategies
In the case where integrating MEMS with electronics, f or example, CMOS, is a
necessity, there are several basic ways in which electronics and MEMS processes
can be integrated: (1) fabricate the CMOS first and then fabricate the MEMS; (2)
fabricate the MEMS first and then fabricate the CMOS; or (3) interleave the process
flow. The CMOS first approach usually starts with a commercially produced CMOS
wafer. It is then postprocessed to produce the MEMS devices. The benefits of this
approach are that the CMOS can be made cheaply in a commercial foundry that
uses the most up-to-date CMOS process technology, and it also allows the MEMS
device to be fabricated directly on top of CMOS circuitry. The main drawback is that
this approach restricts the MEMS processing to materials and thermal cycles that
are consistent with the already completed CMOS circuitry. Other challenges with
this approach are the ability to lithographically align the MEMS to the underlying
CMOS circuitry with high accuracy and the ability to make electrical connections
from the microelectronics to the MEMS devices.
The MEMS first approach allows much more flexibility in the MEMS process
flow than the alternatives for an integrated MEMS process s equence. However, it
then requires a circuit process to be performed on a preprocessed and potentially
nonflat wafer. Such a process often requires physical partitioning of the MEMS and
circuit areas and methods such as CMP to provide a uniform flat area for circuit
processing. It also requires that the MEMS materials used and the wafer cleanliness
be consistent with introduction into a circuitry line (see Section 14.5.2).
An interleaved integration process has the benefit of the greatest level of process
flexibility. The process can be intricately tailored to the specific needs of the device
to be constructed. This may or may not lead to the most efficient process solution,
but in general it will lead to the smallest system footprint. However, this flexibil-
ity is at the expense of maximum integration complexity, higher development cost,
and longer development times. And because it does not force the discipline of a full
circuit/MEMS partitioning, it has the highest likelihood of leading to unforeseen
process interactions. In addition, it is inconsistent with fabrication in commercial
circuit foundries. Thus, the process must be supported without the economies of
scale and ongoing improvement associated with standard foundry processes. For
example, polysilicon is very commonly used as the main structural material for
MEMS devices. However, the thickness of polysilicon in MEMS fabrication is
typically much thicker than that used in the fabrication of IC devices. Therefore,
instead of developing different process recipes for IC and MEMS, it is common for
14 MEMS Process Integration 1067
microfabrication foundries to deposit polysilicon multiple times for MEMS using
existing IC recipes to achieve the required thickness. This example illustrates that
MEMS fabricators often strive for simplicity in process development because this
helps to reduce errors and hence, increase the quality and the yield, even though
such simplicity may not yield optimal properties.
The pros and cons of the approaches to integrate MEMS with microelectronics
have been debated for more than a decade. The first commercially viable inte-
grated MEMS process technology was developed by Analog Devices Inc. in the
early 1990s (see Section 14.8.3). It is an interleaved process flow where the MEMS
process steps are integrated into a standard BiCMOS process flow. This process
has been in production for automotive inertial sensor products for over a decade.
However, as MEMS moved into the commercial marketplace, which constantly
requires lower-and-lower-priced products, this process technology has become com-
paratively too complex and costly. But for higher-performance, higher-cost sensors
it remains a viable process. This example indicates the core conclusion in the MEMS
integration debate; that is, the integration strategy of choice needs to balance the
requirements of performance, size, and cost. No one approach is inherently better
than the others. The decision of which approach to pursue requires careful system-
level design thinking as was discussed at the beginning of this section. As sizes and
costs for MEMS products continue to shrink, the premiums paid for the added per-
formance and flexibility of integrated processes are expected to become more and
more difficult to s upport.
14.7 Design for Manufacturability
14.7.1 Overview
The performance of any MEMS device is strongly linked to the device design, the
fabrication process sequence, the package and assembly methods, and to the envi-
ronment in which the device is used. As a consequence, the variations associated
with all of these areas must be taken into account in both the system-level design
and the MEMS device-level design. Unfortunately, design for manufacturability
is not an easy thing to either describe or teach. It requires a deep understanding
of the device subsystems and a thorough multidomain thinking process. In short,
it requires considerable experience to do well. Nevertheless, there are some rec-
ommended practices that can be employed that will allow a MEMS developer to
achieve a basic level of design for manufacturability which we cover in this section.
The basic goal in designing for manufacturability is to desensitize the system’s
behavior from the manufacturing variations. Therefore, the first requirement is to
understand where the manufacturing variations originate. For example, the manu-
facturing variations that are typically most important in MEMS are the geometric
variations caused by the inherent inaccuracies of the fabrication processes. There
are three major s ources for geometric variations: planar dimension changes (from
1068 M.A. Huff et al.
lithography and etching), planar location offsets (from misalignment), and vertical
dimension changes (from thin-film or substrate thickness variation).
Consider the lithographic processes that produce the inplane geometry of most
MEMS devices. In general, this lithography is performed using a patterned mask in
optical equipment that transfers the desired pattern to a chemical photoresist on the
device wafer. This process has limited resolution due to the fundamental resolution
of the mask and the f ocusing ability of the optical system. Moreover, there will be
alignment or registration errors between the mask and the features on the substrate
that are used to align to the mask. The geometric resolution is further reduced by the
optical and chemical properties of the photoresist material. In addition, the underly-
ing material layer that is to be patterned will not have a perfectly uniform thickness
across the substrate. And finally there is the behavior of the etch process itself to
transfer the mask pattern into a layer on the substrate. No etch process is perfectly
anisotropic and therefore there will invariably be some difference between the mask
and the underlying etch profile. In practice, the inaccuracy of the transfer between
the CAD drawing of the design and the actual as-fabricated structure is the cumu-
lative sum of these collective errors. The idea of design for manufacturability in
this context is to understand this cumulative sum of errors and to develop a device
and system design that is as insensitive to these variations as possible and meets
the required manufacturing yields, which in turn will be dependent on the product
performance requirements.
Understanding the source and magnitude of manufacturing variations that come
from a multitude of physical processes can be extremely difficult. The fundamen-
tal methods employed to understand these variations are a good understanding of
processing technologies, a good quality statistical data-gathering mechanism, and
appropriate modeling to connect design expectations to physical behavior. The
purpose of the remainder of this section is to provide a high-level review of the
major areas of MEMS fabrication that often result in device variations that can
degrade device performance and manufacturing yield. We also provide some general
recommendations regarding design for manufacturability at the end of this section.
14.7.2 Device Design for Manufacturability
The planar dimensions in most MEMS devices are defined by a photolithographic
process. This process typically has three pattern transfer steps: from layout database
to mask, from mask to photoresist, and from photoresist to the desired layer pat-
tern, usually through an etching process. At each step there can be both registration
and scaling errors. The result of these errors is that the MEMS device as fabri-
cated will not be a perfectly precise representation of the device design as drawn
in the mask layout in either its dimensions or shape. Significantly, there is a very
strong coupling between device design for manufacturability and process design for
manufacturability (see below).
The key to designing for manufacturing is to experimentally understand the vari-
ations observed in the fabrication processes and feed them back into the device
14 MEMS Process Integration 1069
design and models so as to scale the dimensions accordingly. For example, if
one is designing a comb-finger-based variable capacitance structure, the width of
the gaps between the fingers i s directly proportional to the capacitance. A typical
photolithography-defined pattern followed by a chemically based etch process will
result in comb-fingers that are slightly narrower than as drawn in the mask layout.
Moreover, the amount by which the comb-fingers are thinner will vary from device
to device, from wafer to wafer, and from lot to lot.
Understanding the mean and standard deviation of the as-etched comb-finger
width allows the designer to translate this geometrical variation to a device behavior
and performance variation. This understanding of performance in light of manufac-
turing variations gives the designer the information on which to develop methods to
desensitize the design to these variations. In the current example, imagine that the
comb-finger variable capacitor is part of an accelerometer whose mechanical stiff-
ness is formed from the same material layer as the comb-fingers. In that case the
same manufacturing variation that causes a reduced sensitivity due to an increase in
the comb-finger gap may also result in an increased sensitivity due to reduced sus-
pension stiffness. Careful design can partially balance these effects and desensitize
the design to this manufacturing variation [2].
Another way to desensitize the fabrication variation is to avoid using the unde-
sirable aspects of a fabrication process to define a device’s critical dimensions. For
example, the dry etching sidewall is typically somewhat vertical, but the smooth-
ness and sidewall angles are usually not well controlled. In the case of a device
design requiring a perpendicular sidewall with 0.5
◦
variation or mirrorlike sidewall
to achieve the critical performance, it will take an enormous amount of process
development effort to obtain these process requirements and therefore would not
be considered a robust design. Similarly, if the thickness variation in a sacrificial
silicon oxide layer is critical to the performance, a robust design at the device level
and system level should accommodate the resulting thickness variation expected
from the process technology used (a few percent thickness variation is common for
LPCVD). When considering process design for manufacturability, a thermal oxida-
tion process will typically exhibit much less thickness variation than either LPCVD
or PECVD processes. Thus, we can consider a thermal oxide process that mini-
mizes the thickness variation as a robust design choice if that would desensitize the
device’s behavior from thickness variations.
14.7.3 Process Design for Manufacturability
Given the strong coupling between design and fabrication in MEMS development, it
should not come as a surprise that the methods for understanding and desensitizing
the device performance to geometric variations due to processing methods over-
lap the issues discussed in the previous section. Building on the example discussed
above of making comb-fingers in a material layer, the manufacturing variations
in the fingers will also be strongly dependent on the process methods used to
1070 M.A. Huff et al.
implement the fingers. For example, the amount of lateral etch observed in a material
layer (i.e., the amount of undercut of the masking layer) will vary depending on the
material used in the layer, the type of etch process used (both equipment and process
recipe), the depth of etch, the amount of overetch required, and loading effects due
to the amount of substrate area being etched.
Most wet chemical etchants are isotropic and will undercut the masking layer
very significantly during an etch process. In comparison, RIE, particularly ICP RIE
processes s uch as DRIE, are highly anisotropic and therefore the amount of under-
cutting of the mask will be greatly reduced. In addition, because the dry etch r ate
varies within the wafer and from wafer to wafer, it would be difficult to control etch
depth using a timed etch as a robust design. As a result, the design with half-etched
depth as the critical parameter may have a large variation.
Etches of all types have a characteristic called “loading.” This refers to the effect
on the material etch front due to the presence or lack of adjacent material also being
etched. The etch of a finely spaced pattern of lines and spaces will be different than
the etch of a material edge with no other etch faces in the local area. One way
to minimize the loading effect is to design a layout with the same etching size so
that the etching rate is approximately the same everywhere. For example, if 10 µm
are the desired etch feature size, all patterns are created by etching a 10 µmwide
contour. Another way is to have at least 15% of overetch to allow complete etching
even at the smallest feature size. It would depend on the side effect of overetching
to determine which way would give better results in a given situation.
As with the planar dimensions described above, variations in material thick-
nesses can have a strong effect on device performance. In many MEMS processes,
the thicknesses of the material layers are highly dependent on the type of process
employed to deposit the layer. For example, many thin-film deposition methods,
such as LPCVD and PECVD have an across-wafer thickness nonuniformity of at
least a few percent or more. Additionally, there will be some variation from the
nominal film thickness desired and the actual thickness after deposition. Similarly,
methods of wafer bonding and thinning-back to create single-crystal silicon layers
having a thickness of a few microns or more, can often have a variation from wafer
towaferofatleast0.5µm or more, which can translate into relatively large relative
tolerances for thin device layers.
The manufacturing variations in the critical dimensions of MEMS devices will
also be highly dependent on the process sequence that is used to implement the
MEMS device. That is, all processing steps before and after, and the processing step
used to define a critical layer’s dimensions may also have an effect on the dimen-
sions of that layer and must be considered. Therefore, as can be appreciated, there
are truly myriad complicated physical mechanisms that can give rise to geometric
manufacturing variations in MEMS. The key to good design for manufacturability is
to fully understand these variations in all of the key dimensions with the potential to
affect the device performance. Developing this understanding requires considerable
data gathering and statistical analysis.
In addition to geometric variations, MEMS devices are subject to significant
variations in material properties. Typical properties with significant variations are
14 MEMS Process Integration 1071
mechanical properties, such as the residual stress, stress gradient, elastic modulus,
and electrical properties, such as the conductivity. Again, the key to good design is
to fully understand the variations in all the key dimensions that affect device per-
formance. Good process design can improve manufacturing variations caused by
material variations. For example, a material’s elastic modulus is intimately linked
to its crystal structure. To obtain repeatable material properties, the process must
be designed to produce repeatable material morphology. In addition to repeatability,
the material properties can be engineered to be more or less isotropic, based on the
uniformity of the material structure.
Another area that is closely linked to material properties is a film’s stress state.
This is mostly relevant to released MEMS structures, where the stress state is again
strongly dependent on the film’s crystal structure. In particular, variation of the
crystal structure through the thickness of the film will cause bending moments,
which cause the released structure to curl. This curvature can vary widely with
small changes in the material’s morphology. Thus, it can cause large manufacturing
variations. Design for manufacturability requires careful process design to deposit a
uniform film and anneal the film to reduce its residual stress, as well as device design
to reduce the sensitivity of the device’s performance to variations in curvature. As
this discussion demonstrates, the design of a material deposition process is much
more complicated than simply getting the desired thickness of a given material.
14.7.4 Precision in MEMS Fabrication
It is helpful at this point to discuss in general terms the relative precision of MEMS
manufacturing methods. It is often incorrectly thought that MEMS allows the fabri-
cation of microdevices with high levels of “precision.” This is not the case because
in general the relative tolerance, expressed as the ratio of the variation of the dimen-
sion of a critical element normalized to the absolute dimension of that same element,
is far less precise than that which is routinely obtained in macroscale machining pro-
cesses (i.e., that which is readily available in a typical machine shop). For example,
it is quite easy t o go to a machine shop and order a cylindrical drive shaft that a
machinist can make to a fairly precise tolerance using standard machining tools and
processes such as a lathe (Fig. 14.9). Let’s say that the design required that the shaft
have a nominal diameter of 4 in. (100 mm). The machinist would easily be able to
make this shaft with a tolerance within ±1mil(±25.4 µm) or better. This translates
into a relative tolerance of 0.0254%.
In comparison, let us examine the relative tolerance of a MEMS device criti-
cal element such as the width of a surface micromachined resonator beam that is
suspended between two anchors affixed to the substrate surface (Fig. 14.10). Let
us assume that the desired design width of the resonator is 5 µm. A typical varia-
tion that would be seen in this dimension using standard micromachining methods
would be around ±0.5 µm or more. This translates into a relative t olerance of the
MEMS device of 10% or nearly 400 times worse than obtainable with macroscale
machining techniques! Moreover, depending on the physics of the device the relative
1072 M.A. Huff et al.
4 inches +/
–1 mil
Cylindrical Steel Shaft
Macroscale Machine Tool
Relative Tolerance =
25.4 × 10
–6
m
100 × 10
–3
m
×
100%
=
0.0254 %
Fig. 14.9 Illustration of relative fabrication tolerances using macroscale machining methods
(Reprinted with permission, copyright MEMS and Nanotechnology Exchange)
5 um ± 0.5 um
Feature
Size
Precision
5 um
0.5 um
= 10%
QuickTime™ and a
decompressor
are needed to see this picture.
Anchor
Anchor
Suspended MEMS Resonator Beam
Relative Tolerance (Precision) =
Fig. 14.10 Illustration of the plan view of a resonator beam clamped at both ends (at the anchors)
and suspended along its length, and showing the relative fabrication tolerances obtainable using
micromachining methods
tolerances will often have a larger than simple linear impact on the performance of
a MEMS device. Specifically, the order of the physics of the MEMS device can
magnify the impact of the lack of precision on the device performance.
For example, the volumetric flow rate in a MEMS microchannel scales to the
fourth power of the hydraulic diameter of the microchannel at a constant differential
pressure assuming laminar flow. Therefore, any lack of precision in the diameter of
the microchannel will have a fourth-order effect on the flow rate. Similarly, the
stiffness of a beam is dependent on the thickness of the beam cubed if the motion
is orthogonal to the substrate surface as in the example of the suspended resonator
example in Fig. 14.10. The deflection of a thin membrane clamped along each side,
which is a commonly used configuration for implementation of pressure sensors,
varies to the fourth power of the edge length of the membrane and inversely to the
cube power of the membrane thickness. As can be appreciated, the cumulative effect
of all these variations can be very significant. It is also important to note that for
14 MEMS Process Integration 1073
most MEMS machining processes, the dimensional control gets worse as the size of
the critical elements is made smaller and therefore the precision decreases. As these
examples serve to demonstrate, MEMS allows the implementation of miniaturized
mechanical devices, but does not allow the dimensions of the devices to be made
precisely.
The lack of precision in MEMS manufacturing tolerances has huge implica-
tions throughout MEMS technology and business. As shown in Fig. 14.11,the
manufacturing process for the production of MEMS is essentially an open-loop
manufacturing process. That is, the fabrication process sequence and the parame-
ter settings of the process sequence (i.e., tool settings, process recipes, etc.) are first
defined and set and then the MEMS devices are fabricated. Quality control during
the manufacturing process typically involves performing metrology measurements
of the critical dimensions using statistical sampling on various devices and wafers
at preselected events during the process sequence. Only at the very end of the man-
ufacturing process is the device performance measured. Any deviations seen in the
metrology measurements of the critical dimensions taken during the manufacturing
process can be used to tweak the process, but may come at the loss of the wafers
partially processed up to that point in the process sequence.
Define process sequence
and tool parameter settings
Perform metrology
on a sampled basis
Measure device
performance
Fabricate devices
Fig. 14.11 Open-loop manufacturing process typically employed in MEMS production
More important, the ultimate performance is not known until after the manufac-
turing process for a batch is completed. This means that whole wafer lots can be
lost if the performance falls out of the acceptance range. Additionally, there is sig-
nificant time and cost required to adjust the manufacturing process in an attempt to
increase the number of devices with an acceptable performance level (i.e., obtain a
higher yield).
Ultimately the goal of MEMS manufacturing is to tighten the spread of the
variations in the critical dimensions and to reduce the amount of bias offset.
This is portrayed in Fig. 14.12 wherein in Fig. 14.12a is shown a Gaussian bell
curve that would be the expected statistical variation seen in a large sampling of
MEMS devices with respect to their performance levels. We have superimposed an
acceptance range, that is, the range of devices having a performance level that is
acceptable for a given application or product. As shown in Fig. 14.12a, the statis-
tical variation is rather large (i.e., the Gaussian curve is wide) and there is a bias
offset, that is, the centerline of the Gaussian curve does not line up with the center-
line of the acceptance range. Consequently, the overlap of the acceptance range and
Gaussian curve is rather minimal and the manufacturing yield will be very low. In
contrast, the Gaussian curve of Fig. 14.12b has much less statistical spread (i.e., the
width of the Gaussian curve is minimal) and the Gaussian curve centerline coincides
with the acceptance range centerline resulting in a very high manufacturing yield.