Ghodssi R., Lin P., MEMS Materials and Processes Handbook

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1024 P. Lin e t al.

of defects and improving device yield, when combined with an optimized polishing

process [208, 245]. While the purpose of CMP cleaning is to efﬁciently remove

contaminants on a polished wafer, it also must not degrade any material properties.

Although defect requirements in MEMS fabrication are less stringent than those

encountered in IC manufacturing due to larger feature sizes in MEMS, post-CMP

cleaning still plays a key role in ensuring high production yields.

There are two types of post-CMP cleaning: contact mode and non-contact mode.

Double-sided polyvinyl alcohol (PVA) brush scrubbing is the most widely used con-

tact cleaning process. As shown in Fig. 13.62, the wafer is sandwiched between a

pair of double-sided brush scrubbers, so that both sides of the wafer are cleaned

simultaneously. The efﬁciency of the process is tunable by adjusting the scrubbing

speed or by adding chemical additives to the cleaning solution.

Non-contact cleaning methods include using megasonics or spray processes to

remove contaminants from the wafer’s surface [247]. Many cleaning equipment

suppliers offer systems utilizing a combination of contact and non-contact cleaning,

increasing cleaning efﬁciency.

A variety of wet-cleaning chemicals are used in semiconductor manufacturing.

Table 13.14 lists examples of cleaning solutions. As described in the table, cleaning

solutions formulated with different chemicals are used for different applications.

Cleaning solutions are also commonly formulated with organic acids, such as oxalic

acid, citric acid, and various surfactants. Organic acids can serve as complexing

agents to dissolve metal contaminants into the solution. Another function of organic

acids is to control the surface zeta potential by adjusting the pH of the solution [248].

Fig. 13.62 Post-CMP

cleaning system. (a)

Brush-scrub cleaning. (b)

Appearance of PVA brush

[246]. Reprinted with

IEEE

13 Surface Treatment and Planarization 1025

Table 13.14 Typical cleaning solutions

Cleaning

solution Composition Typical application

APM (SC1) NH

OH/H

O Removal of organic contaminants and particles

HPM (SC2) HCl/H

O Removal of metallic ions; surface passivation by

native oxide formation

DHF HF/H

O Removal of native oxide ﬁlm and metallic ions

SPM H

Removal of organic contaminants and metallic ions

Table 13.15 Summary on post CMP cleaning processes for various materials

CMP Typical defects Technique Chemicals Consideration

Oxide Slurry particles,

scratches

Brush scrubbing,

spray

OH, HF Over exposure to

cleaning solution

may deepen

scratches

W Slurry particles,

scratches,

residual metal

Brush scrubbing,

bufﬁng

DHF Removal of slurry

residual from

recessed plug

STI Slurry particles,

organic

contaminants

Brush scrubbing NH

OH, HF Removal of

contaminants

from both oxide

surface and nitride

surface

Poly-Si Pad debris,

Organic

contaminant

Brush scrubbing SC1 Avoiding water

marks

Cu/low-k Slurry particles,

organic

contaminants,

residual metal

Brush scrubbing BTA

,NH

OH,

TMAH

Citric acid,

Oxalic acid

Avoiding corrosion

BTA: Benzotriazole; TMAH: Tetramethylammonium hydroxide

Surfactants are widely used in cleaning solutions to modify surface interactions by

inﬂuencing the surface zeta potential [249].

Speciﬁc concerns exist for post-CMP cleaning, due to the interactions between

slurry and different surfaces. Table 13.15 lists common cleaning solutions and

concerns for typical materials used in semiconductor manufacturing.

13.7.6 Case Study

CMP t echnology has been applied in MEMS fabrication for many years. CMP can

be used to ﬂatten sacriﬁcial layers, such as oxides, and improve the uniformity of

oxide across a wafer’s surface [250]. The 5-level polysilicon surface micromachin-

ing technology developed by Sandia National Labs would be virtually impossible

1026 P. Lin e t al.

without planarization [250, 251]. In MEMS-CMOS integration, MEMS wafers can

be bonded to COMS wafers with Al as the interconnect between the two wafers.

After the Al sputtering process, Al CMP can be used to remove excess Al and

deﬁne the contact via areas, ensuring good wafer bonding [252]. CMP can also

serve as an alternative to reactive ion etching (RIE) for patterning thin ﬁlms. In one

study, ZnO was deposited onto a patterned Si surface using radio frequency (RF)

sputtering and CMP was used to remove excess ZnO in un-patterned areas [253].

Multi-layered poly-silicon carbide (poly SiC) for micro-mirrors has also been fab-

ricated with CMP on poly SiC, using patterned silicon oxide as a sacriﬁcial layer

[254, 255]. A few examples of CMP processes used in MEMS fabrication will be

discussed in the following case studies.

13.7.6.1 Case Study 10: Magnetic Microdevice

Most MEMS transducers are driven electrostatically, mainly because of the ease of

fabrication and integration [256, 257]. However, magnetic microdevices are also

of interest, due to their unique advantages including their capability for main-

taining large forces over long distances, low voltage operation, no snapdown, low

hysteresis, and linear torque-current relationship [258]. Magnetic microdevices are

used in applications such as optical switches, magnetic microparticle manipulation,

microﬂuidic mixing, and micro-mirror actuation.

The key component in a magnetic microdevice that requires CMP is the con-

ductive microcoil. Typically, microcoils are fabricated by depositing a thick ﬁlm of

conductor material onto the Si surface with/without a core. Figure 13.63 shows a

typical process ﬂowchart for the fabrication of an inductive coil with a copper con-

ductor. In this case, the coil is fabricated with damascene technology. A few microns

of copper are plated onto the etched pattern, followed by CMP to achieve a pla-

nar surface. Similar to copper interconnect CMP in microelectronic manufacturing,

dishing and defects such as erosion pits are the main concerns in this CMP pro-

cess. Uniformity is another important consideration for process optimization, since

coils are fabricated on wafer level. Using a stacked pad, such as IC1000/SUBA IV,

is one option to avoid severe dishing and erosion and to achieve good uniformity.

Figures 13.64 and 13.65 shows various designs of conductive coils fabricated on a

wafer via the CMP process. In Fig. 13.65, a core is incorporated into the center of the

conductive coil to enhance magnetic ﬁeld intensity and to increase the magnitudes

of magnetic ﬁeld gradients in that area.

13.7.6.2 Case Study 11: A Drug-Delivery Probe with an In-line Flow Meter

A silicon drug delivery probe integrated with an in-line ﬂowmeter is discussed in

this case study [260]. The silicon probe includes a microchannel built into the probe

for drug delivery. A polysilicon-based in-line thermal ﬂowmeter is positioned on

top of the microchannel. As shown in Fig. 13.66, a triangular channel is formed

by layered LPCVD oxide/nitride/oxide sidewalls (labeled as dielectrics) and a

13 Surface Treatment and Planarization 1027

SiO

(wet oxide)

Adhesion Promoter

Polyimide

SiO

(sputtered)

(a)

(b)

(c)

(d)

(e)

(f)

(g)

(h)

Fig. 13.63 Typical process ﬂow for coil fabrication [259]. Reprinted with permission. Copyright

2008 IEEE

lightly-doped polysilicon resistor is formed on a dielectric diaphragm over the

ﬂow channel. Doped polysilicon is used to connect the resistor. A vacuum gap

of 2 μm is used to cap the dielectric window to minimize heat escape to the sur-

roundings and maximize heating efﬁciency. During the operation, constant current

is applied to heat the sensor. When liquid ﬂows through the channel, convective

heat transfer reduces the sensor temperature, leading to increased sensor resis-

tance [260, 261]. Compared to boron-doped silicon sidewalls for the probe [261],

the dielectric sidewalls offer about 20% better heating efﬁciency and ﬂowmeter

sensitivity.

Figure 13.67 shows the processing steps with a combination of trench reﬁll and

CMP t o fabricate microﬂuidic channels with dielectric sidewalls. A triangular trench

(at least 15 μm wide) is formed by ethylenediamine pyrocatechol (EDP) etching,

1028 P. Lin e t al.

Fig. 13.64 Coil structure on

a wafer after CMP [259].

Reprinted with permission.

Fig. 13.65 Aspiral

micro-coil with a magnetic

pillar in the center [258].

Reprinted with permission.

Fig. 13.66 The structure of a

vacuum-isolated thermal

in-line ﬂowmeter located on a

dielectric diaphragm over the

microchannel [260].

Reprinted with permission.

followed by shallow boron doping and deposition of dielectric layers as the side-

walls. Polysilicon was then deposited (about 13 μm) to ﬁll the trench as a sacriﬁcial

material, and a damascene CMP process was used to planarize the top surface so

that polysilicon remained only within the channel– that is, polysilicon in non-trench

areas was polished down to the oxide layer. A layer of masking oxide was deposited

13 Surface Treatment and Planarization 1029

Fig. 13.67 Fabrication process for a drug delivery probe with in-line ﬂowmeters based on trench

to cover and pattern the trench, and the sacriﬁcial polysilicon was removed using

EDP to form the channel. The channels were then sealed with LPCVD dielectric

materials.

After the channels were sealed, a polysilicon heater was positioned on top of

the channel’s surface, followed by regular surface micromachining to complete the

in-line thermal ﬂowmeter. The main purpose of the CMP process in this case was

to remove 13 μm of polysilicon. Selectivity of polysilicon over oxide during this

CMP process is critical. Another key consideration is dishing, which must be con-

trolled to ensure ﬂatness of the top surface of the channel. Highly selective slurry for

polysilicon over silicon dioxide has been reported for use in this application [262].

By adding additives such as arginine into colloidal- or ceria-based slurry, removal

rates up to 550 nm/min can be achieved for polysilicon. The selectivity ratio of

polysilicon over silicon oxide is about 130.

13.7.6.3 Case Study 12: Nanomechanical Optical Devices

Integrated optical devices have been designed and fabricated to take advantage of

the fact that the effective refractive index of a waveguide can be modulated by a

movable element that is driven into the evanescent ﬁeld over a distance of about

100 nm [263]. The applications of such devices include optical intensity modulators,

tunable ﬁlters, and optical pressure sensors. A schematic cross-section of the device

is shown in Fig. 13.68. The waveguide is fabricated at the lower wafer, and the

moving element is positioned on the top wafer using KOH etching. The gap between

the moving element and the waveguide is determined by the thickness of the PECVD

1030 P. Lin e t al.

SiO

spacer layer on top of the waveguide. Prior to wafer bonding, the PECVD

SiO

spacer layer must be polished, since it is critical for controlling gap distance

and smoothness.

A MECAPOL E460 tool was used with Semisphere 25 slurry and UR 100 pad for

the CMP process. PECVD SiO

(1 μm) was deposited and patterned prior to CMP.

Processing conditions used were a working pressure of 14.5 psi and a rotation speed

of 60 rpm; these conditions resulted in a removal rate of 300 nm/min for PECVD

SiO

. Atomic force microscopy (AFM) data showed that the root mean square

roughness was reduced by a factor of 10 (from 2.2 to 0.2 nm) after 30 s of polishing.

After CMP, the wafer underwent brushing, DI water rinsing, and RCA cleaning to

remove residual slurry particles and possible sodium hydroxide contamination.

Light in

Light out

SiO

Membrane Element

Optical waveguide wafer Waveguide Bonding interface

Fig. 13.68 Schematic cross section of the integrated optical nanomechanical device [263].

Fig. 13.69 Model of

electroforming and metal

CMP

13 Surface Treatment and Planarization 1031

13.7.6.4 Case Study 13: CMP of SU-8/Permalloy Combination in MEMS

Devices

Polymer materials are widely used in MEMS fabrication to create high aspect ratio

structures. This case study investigates the applications of CMP for planarization

of electroplated permalloys (NiFe 81/19) in micromolds using epoxy SU-8. This

polymer serves as a stopping layer during CMP, and remained in the structure

as an insulation layer. The SU8/permalloy combination was designed to fabricate

magnetic MEMS devices.

Figure 13.69 shows a schematic view of the cross-section of a typical magnetic

MEMS device. A SU-8 micromold of about 20 μm was patterned on top of a suit-

able plating base. The NiFe was electroplated onto the microforms, ﬁlling the molds

completely. The NiFe overburden had to be polished to achieve surface planarity.

In order to selectively ﬁll the SU-8 micromolds, a novolac photoresist mask was

applied before electroplating. Polishing conditions and slurry information are listed

in Tables 13.16 and 13.17.

The mechanical properties of SU-8 depended on post-bake t reatment. In this

study, the polymer was treated at 95, 120, and 150

◦

C. Figure 13.70 shows the cor-

relation between removal rate and polishing pressure for SU-8 treated at different

temperatures. Polymers treated with higher post-bake temperatures showed better

resistance to abrasion, and thus had low material removal rates. An AFM study

showed scratches on the polymer surface, indicating mechanical abrasion during

polishing. However, the overall surface quality met the requirements for the intended

application.

The removal rates of permalloy under different pressures are shown in Fig. 13.71.

The results indicate that permalloy has about half of the removal rate of SU-8 baked

at 150

◦

C. AFM analysis showed mottled free surfaces, indicating well balanced

chemical and mechanical effects during polishing. Based on these polishing rates

of SU-8 and permalloy, optimal CMP conditions were selected for the NiFe/SU-8

Table 13.16 Polishing

conditions for NiFe

Polishing conditions

Polisher Peter Walters 3R40

Platen diameter 400 mm

Pad IC1400 stacked

Platen speed 18 rpm

Carrier speed 18 rpm

Slurry ﬂow 15 ml/min

Table 13.17 Slurry

speciﬁcations for NiFe CMP

Slurry speciﬁcations

Abrasive particle Al

Median particle size 225 nm

pH at 25

◦

C4.1

Abrasive content 6.9 wt%

1032 P. Lin e t al.

Fig. 13.70 SU-8 removal

rate as a function of polishing

pressure for different hard

bake times [264]. Reprinted

with permission. Copyright

2003 Elsevier

Fig. 13.71 Permalloy

removal rate as a function of

polishing pressure [264].

Reprinted with permission.

structures. Step height was reduced to about 20 nm after planarization, which was

sufﬁcient for the intended application of the device.

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