Ghodssi R., Lin P., MEMS Materials and Processes Handbook

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1014 P. Lin e t al.

features include ease of handling during use and in waste disposal, long-term stabil-

ity, and low sensitivity to pattern density and line width effects (which may vary by

up to 5 orders of magnitude in different patterned areas on a single wafer).

CMP slurries can be generally categorized into two groups: dielectric slurries

and metal slurries. The most commonly used dielectric thin ﬁlm in IC and MEMS

processing is silicon oxide. Slurries for oxide CMP processes have been devel-

oped from those used in the optical industry, in which silicate glasses must be

ﬁnely polished to fabricate optical devices such as lenses and mirrors. Normally,

oxide slurries consist of a colloidal suspension of ﬁne fumed silica particles with

chemical additives for pH adjustment, typically KOH or NH

OH. Researchers

have also concentrated their efforts on developing ceria-based oxide slurries. Ceria

interacts chemically with oxide at a higher rate than silicon oxide does, and thus

ceria slurries are able to produce high material removal rates with low abrasive

content.

Metal slurries typically contain abrasive particles such as silica, and a number

of chemical additives such as oxidizers (H

, Fe(CN)

), inhibitors, complexing

agents, surfactants, and polymer additives. As the minimum feature size shrinks, the

tolerance for CMP defects drops dramatically. Since hard abrasives like silica can be

a signiﬁcant source of defects and dielectric loss due to the aggressive mechanical

abrasion, researchers have investigated so-called “hybrid abrasive systems,” i.e. the

incorporation of silica with ﬂexible polymer particles [229]. Pure polymer particles

are also intensively studied as potential replacements for conventional inorganic

abrasives [230].

Table 13.12 summarizes the effect of slurry variables on CMP performance. This

information can be used as a reference when a slurry must be tuned to meet speciﬁc

performance requirements.

Table 13.12 Effect of slurry variables on CMP performance

Slurry variables Effect

pH Dissolution rate of the surface being polished or polishing debris;

stability of the abrasive suspension

Buffering agents Prevent pH drifting

Oxidizers Induce reduction-oxidation reaction on substrate (metals), leading

to metal dissolution or surface ﬁlm formation

Complexing agents Enhance dissolution of the surface (metals) being polished or

polishing debris

Viscosity Transport of abrasive and chemicals to and from wafer surface

Slurry abrasive type Abrasion models

Slurry abrasive size Removal rate, surface quality (scratches)

Slurry abrasive hardness Removal rate, surface quality

Slurry abrasive

concentration

Removal rate

Slurry stability Abrasive agglomeration, surface damage

13 Surface Treatment and Planarization 1015

13.7.3.1 Summary of Slurry and Pad

In order to meet speciﬁc requirements for MEMS and microelectronic fabrication,

commercial suppliers of slurries and pads have developed various dedicated prod-

ucts. Normally, slurries optimized for use in microelectronics manufacturing can be

adopted for use in MEMS CMP. However, due to the different wafer structures and

materials, these slurries cannot generally be used as-is in MEMS fabrication. Further

optimization is required to adapt slurries designed for use in microelectronics man-

ufacturing for use in MEMS. Pads used in MEMS fabrication, meanwhile, are

essentially the same as those used in microelectronics manufacturing. Table 13.13

lists some information about commercial slurries and pads used in MEMS polishing.

13.7.4 Polishing Considerations for Different Materials

The main concerns in CMP processes are polishing rate, planarization capabil-

ity, within die non-uniformity, within-wafer non-uniformity, wafer-to-wafer non-

uniformity, removal selectivity, defects, and contamination. Though some of these

issues, such as defect control, are common to all CMP processes, each CMP pro-

cess also has speciﬁc issues. In general, CMP processes in MEMS fabrication can

be grouped into three areas: dielectrics (including semiconductors), metals, and

polymers. In this section, major considerations for each of these materials will be

discussed.

13.7.4.1 Rate Comparison and Selectivity

In many CMP applications, it is desirable that material removal should continue

only until a certain interface has been reached, at which point the process should

stop. Therefore, a crucial consideration in slurry development is the differential

removal rate for the target and underlying layers. For example, in copper polishing,

an important interfacial concern is erosion: removal of the supporting inter-layer

dielectric (ILD) after the barrier layer has been removed [231]. Erosion is depen-

dent on ILD polishing rate, barrier removal rate selectivity, pattern density, and pad

hardness. As shown in Fig. 13.58, features with high pattern density are under high

local pressure due to the reduced supporting area for the polishing force. Therefore,

smaller features experience a higher material removal rate. Consequently, increased

ILD exposure time leads to erosion [231]. Erosion can be minimized by improving

slurry selectivity; with enhanced selectivity, the polishing process can effectively

stop when the ILD layer has been reached. CMP processes with endpoint detec-

tion can also reduce erosion by sensing that the ILD layer has been exposed, either

through changes in polishing table current or through optical signals [232]. Endpoint

detection systems improve process control, combatting variations such as pad-to-

pad variations, slurry instability, and pad wear. Erosion in other metal polishing

processes, such as tungsten CMP, has also been studied [233].

1016 P. Lin e t al.

Table 13.13 Pads and slurries for CMP in microfabrication [228]

Material Pads References Slurries References Remarks

Si-oxides

(SiO

, TEOS,

PETEOS, doped

oxides)

IC1000

Series,

Politex

Prima

Rohm and Haas Klebosol



1501-50,

Klebosol



1508-50

Rohm and Haas

EP-MD-8052,

EP-MD-8073

EP-MD-8080,

EP-MD-8090

Cabot

Microelectronics

Fumed silica, for

stack heights ≤

1 μm; colloidal

silica, for larger

stack heights

Planerlite-4000 Series Fujimi

Levasil 50CK/30%, Levasil

50CN/30%, Levasil

100 K/30%

H.C. Starck

SS 25 from Cabot Fraunhofer ISIT

SiN Suba

500,

Politex

Regular

Rohm and Haas Nalco



2360 Rohm and Haas

MH Series Rohm and Haas Eminess UltraSol

M5D4

(main)

Eminess UltraSol

500

(ﬁnal)

Rohm and Haas

Sapphire IC1000

Perforated,

Suba

1250,

Politex

Regular

Rohm and Haas 6 μm/3 μm diamond (1),

1 μm diamond (2),

UltraSol 500 (3)

Rohm and Haas

SiC IC1000

Perforated,

Suba

1250,

Politex

Rohm and Haas Nalco 2360 Rohm and Haas

13 Surface Treatment and Planarization 1017

Table 13.13 (continued)

Material Pads References Slurries References Remarks

Silicon Suba Series, SPM

pads

Fraunhofer ISIT Glanzox series Fujimi

Fixed abrasive pads VTT, 3 M Levasil 50/50%, Levasil

100/45%, Levasil

200/30%-WALM

H.C. Starck

Polysilicon IC1000

Series,

Politex

Prima,

WWP3

Rohm and Haas Klebosol



PL 1509-35,

Klebosol



PL 1509-12,

Klebosol



PL 1618

Rohm and Haas

SS 25 from Cabot Fraunhofer ISIT

Planerlite-6000 Series Fujimi

EP-MP-8010, EP-MP-8188 Cabot

Microelectronics

for stack heights ≤

1 μm

for larger stack

height removal

Germanium Suba

Politex

embossed

Rohm and Haas Nalco



2360 Rohm and Haas

SiGe Politex

Regular,

SPM3100

Rohm and Haas Levasil 50CK/30%-V1,

Levasil 50CK/30%-V2

H.C.Starck Abrasive for metal

slurry formulation

1018 P. Lin e t al.

Table 13.13 (continued)

Material Pads References Slurries References Remarks

Copper IC1000

Series,

VisionPad

Series, Politex

Prima

Rohm and Haas EPL2361 Rohm and Haas

EP-MH-870, EP-MH-883

EP-MM-8042,

EP-MM-8043

Cabot

Microelectronics

for stack height ≤

5 μm

for stack heights ≥5

μm

Planerlite-7000 Series Fujimi

iCue



Slurries from Cabot Fraunhofer ISIT

Tantalum, TaN, TiN IC1000

Series,

Politex

Regular

Rohm and Haas CUS Series, LK Series,

SSA Series

Rohm and Haas

Tungsten IC1000

Series,

Politex

Series,

FBP Series

Rohm and Haas e.g. W2000 from Cabot Fraunhofer ISIT

NiFe IC1000

Series,

Politex

Prima,

WWP3000

Rohm and Haas MSW1500/2000 Rohm and Haas

ZnCu IC1000

Series Rohm and Haas MSW1500 Rohm and Haas

Compol Series Fujimi

Levasil 50/50%, Levasil

100/45%

H.C. Starck Abrasive for slurry

formulation

13 Surface Treatment and Planarization 1019

Table 13.13 (continued)

Material Pads References Slurries References Remarks

AlN Suba

500 Rohm and Haas Nalco



2370 Rohm and Haas

GaAs Suba

embossed,

Suba

500,

OPC6350,

SPM3100

Rohm and Haas Nalco



2360 Rohm and Haas

InP Suba

500,

Suba

SPM3100

Rohm and Haas Nalco



2360 w/bleach Rohm and Haas

LiNbO

Suba

1250,

Politex

embossed

Rohm and Haas

Glass MH Series, Suba

X, GS

Rohm and Haas Ceria based (main),

Nalco



2360 (ﬁnal)

Rohm and Haas

Polyimide EP-MI-8005, EP-MI-8006 Cabot

Microelectronics

alumina based slurry

alumina based, low

defects

1020 P. Lin e t al.

Δh

SiO

Δh

SiO

Δh

SiO

Δh

Fig. 13.58 (a) Regions of low and high copper pattern density (PD); (b) copper polishes faster in

regions of high PD, so the copper in those regions is cleared ﬁrst; (c) consequently, the underlying

dielectric layer SiO

receives more polishing time in regions of high PD and therefore experiences

13.7.4.2 Dielectrics

As an enabling technology for lithography, etching and metallization, oxide CMP

is the most commonly used and studied CMP process [208]. In order to improve

interconnect reliability and yields, global planarization must be achieved in oxide

CMP. In addition to the improvements in lithography, oxide global planarization

also assists in the subsequent etching of the contacts and vias. Global planarization

depends mainly on underlying feature density. A number of studies of oxide CMP

have investigated the effect of the pattern density on global planarization efﬁciency

[234–236]. CMP process variables and consumables were each found to have a sig-

niﬁcant effect on global planarity. Process parameters that affected global planarity

included platen speed, downward force, and carrier speed [234]. Properties of con-

sumables such as pad hardness and ﬂuid dynamics also affected global planarity

[235, 236].

Bulk oxide polishing, such as ILD CMP, does not involve a material interface

as a stopping layer. Therefore, within wafer non-uniformity is solely dependent

on removal rate controls in the CMP process, tool, and consumables. In general,

within wafer non-uniformity is determined by non-uniformities in the removal rate

and in the ﬁlm thickness. On the die scale, the removal uniformity depends on pat-

tern density, while on the wafer scale, the edge effect has a large impact on the

uniformity, as the wafer size increases from 150 to 200–300 mm [237, 238]. It is

possible to manipulate the CMP removal rate distribution to compensate for the

known non-uniformity of the wafer.

Another concern in oxide CMP is the presence of defects. The most com-

mon defect associated with oxide CMP is scratching [239]. Scratches can result

from pad/wafer contact, abrasive particle/wafer contact, and wafer handling errors.

Depending on the size and depth of the scratch, such a defect might cause various

failures, including shorting between adjacent lines if metal ﬁlls in a wide scratch.

Buff CMP processes are used to reduce scratches on the wafer. In buff CMP, wafers

are typically polished under low stress on a soft pad to remove small amounts of

13 Surface Treatment and Planarization 1021

oxide, helping to remove the sharp edges associated with a scratch. Although buff

CMP can improve yields by smoothing scratches, it cannot be used to repair deep

scratches. Therefore, the best option to avoid yield loss caused by scratching is

to eliminate the source of defects from CMP processes and consumables. Another

common source of defects in oxide CMP is contamination of wafer surfaces by par-

ticles or chemical contaminants during the CMP process. Post-CMP cleaning can

be performed to remove these contaminants from wafers.

13.7.4.3 Metals

Tungsten CMP and copper CMP are currently the mainstream fabrication techniques

for metal interconnect structures in semiconductor devices. Tungsten intercon-

nects can be divided into two categories: contacts, which serve as the interconnect

between the front-end of the device and back-end metallization, and vias, which

connect metal layers, as shown in Fig. 13.59. In order to overcome the high

resistance associated with decreasing metal line size, copper is introduced due to

its low resistivity to replace the conventionally-used aluminum in metallization.

Conceptually, tungsten plug fabrication and copper damascene are quite similar.

Figure 13.60 shows the process of forming copper lines and vias using the dam-

ascene technique. Speciﬁcally, oxide is etched to form the patterns for wires and

lines. A barrier layer is deposited to enhance the adhesion of the metal line and to

avoid the diffusion of copper ions into the underlying dielectric layer. Copper is then

deposited, and the overburden of copper is removed with CMP. In both tungsten and

copper CMP, the two main interfacial concerns are dishing and erosion.

Fig. 13.59 Cross-sectional

SEM image of a

representative tungsten plug

between two metal lines

[240]. Reprinted with

CMP MIC

1022 P. Lin e t al.

Fig. 13.60 Damascene and dual damascene technology

In tungsten CMP, dishing refers to the removal of tungsten inside the via below

the ILD surface, while in copper CMP dishing refers to the removal of copper in the

trench below the ILD surface. In either case, erosion is the removal of material from

the supporting ILD after clearing the barrier layer [231]. Figure 13.61 illustrates

the differences between dishing and erosion in copper CMP. Dishing is dependent

on line width [231], copper removal rate selectivity, and pad hardness. At large

feature size, high copper removal rate selectivity for barrier or dielectric increases

13 Surface Treatment and Planarization 1023

Fig. 13.61 Schematic diagram of dishing and erosion in copper CMP

the dishing rate. Softer pads allow the force to penetrate into the trench, which also

leads to dishing. As mentioned in 13.7.4.1, erosion is highly dependent on pattern

density, removal selectivity, and pad hardness.

13.7.4.4 Polymers

In order to minimize interconnection delays, various polymeric low-k dielectric

materials have been introduced in microelectronics [241]. In MEMS fabrication,

a wide range of polymeric materials has been used depending on the speciﬁc

application. For example, polycarbonate (PC) and polyimide (PI) are often used

in biomedical devices due to their suitable interface with biological tissues [242].

Polymethyl methacrylate (PMMA) substrates are used to fabricate microﬂuidic

devices with an inprinting technique [243]. Global planarization is required on the

polymeric layer. The major challenge for the planarization of low-k dielectrics and

other polymers is their inferior mechanical strength and hardness as compared with

silica. This directly affects the CMP process because force and rotation rate must

be reduced to avoid mechanical damage and scratching. Requirements on slurry

chemistry are quite speciﬁc to the polymer substrates, as they depend strongly on

the chemical properties of the material. Furthermore, control of large particles in

the slurry must be more restrictive, because large agglomerates can easily indent

polymers due to their soft nature [244].

13.7.5 Cleaning and Contamination Control

An inseparable part of the CMP process, post-CMP cleaning determines the ﬁnal

defect level on the polished wafer, and thus signiﬁcantly affects the yield. During

CMP, wafer surfaces exposed to the aggressive chemicals and pressures inherent

in the process are easily contaminated with polishing residues, trace metals, organic

additives, and so forth. Resulting modiﬁcations and damage to the wafer surface can

adversely affect the device’s properties and performance. For example, polishing

residue can cause patterning and/or deposition errors in subsequent processes. These

errors may lead to shorts and incomplete circuits in the interconnect. An effective

post-CMP cleaning process can minimize this type of fault, reducing the frequency