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404 DIFFUSION PROCESSES IN ADVANCED TECHNOLOGICAL MATERIALS

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9 Electromigration in Cu Thin Films

Chao-Kun Hu, Lynne M. Gignac, and Robert Rosenberg

IBM T. J. Watson Research Center, Yorktown Heights, New York

9.1 Introduction

Cu wiring in integrated circuits for high-performance chips has been

pursued for many years.

[1–4]

The production of IC chips with Cu inter-

connections has increased each and every year since its initial commer-

cialization in 1997 by IBM.

[5]

Chips with Cu wiring have improved conduc-

tivity, which has resulted in reduced RC time delays for wiring, where R

is resistance and C is capacitance. When IC chip technology is extended

below 0.2-mm dimension, the RC delays from interconnections will con-

stitute a large percentage of the total chip time delay.

[5]

In addition to

reduced resistance, Cu interconnections have longer electromigration

lifetimes compared to chips with the conventional Al(Cu) metalliza-

tion.

[5–13]

Electromigration arises from the motion of atoms under the

influence of intense electric field and current. The imbalance of atomic

flux at some critical sites in metal lines results in the formation of voids

or extrusions, resulting in failure of the chips. Electromigration in Al(Cu)

thin films has been a subject of extensive studies for several

decades.

[14–16]

Investigators have reported that electromigration in Al

thin-film lines is related to grain boundary diffusion,

[16]

interface

diffusion between Al and TiN,

[17]

TiAl

[17, 18]

AlO

[19]

crystallographic

texture,

[20, 21]

solute (Cu) effects,

[22, 23]

and, to a lesser extent, bulk diffu-

sion.

[24]

However, electromigration rules for Cu lines cannot be drawn

from the Al(Cu) experience. In the Al(Cu) case, lifetime increases as

linewidth decreases, because the drift velocity at Al(Cu) dielectric sur-

faces/interfaces is lower than that at grain boundaries, and the number of

grain boundary paths are reduced in a bamboo-like microstructure of fine

lines.

[25]

But electromigration of Cu atoms is mainly dominated by inter-

face transport,

[26, 27]

which is usually faster than grain boundary diffusion.

So the electromigration lifetime in Cu interconnects decreases as the

cross section of line area becomes smaller.

[10]

Modern commercial IC chips, which usually contain four to eight

levels of Cu interconnections, are generally fabricated by a damascene

process,

[5, 6]

which is described in Sec. 9.2. Cu interconnections require

metal liner and insulator adhesion/diffusion barrier layers to form the

Chapter-09 11/29/04 6:50 PM Page 405

multilevel lines and vias.

[28]

The metal barrier layer or liner creates mate-

rial dissimilarities at level-to-level interfaces and is often the cause for

electromigration flux divergence, as long as mass transport through the

liner is negligible. Furthermore, to increase device density and perform-

ance, each generation of IC chips has smaller line/via sizes and higher cur-

rent densities. Interconnects with smaller via size require less time to

grow voids that result in failure. Consequently, the electromigration life-

time for each generation of interconnections is expected to decrease.

[10]

Therefore, electromigration in these newly emerging Cu on-chip inter-

connections becomes increasingly important and has been a popular topic

for research in recent years.

[29, 30]

In damascene interconnection structures, the top surface of a Cu line

is generally covered by an insulator diffusion barrier layer, such as SiN

SiC

, SiC

, or SiC, and the bottom and sides of the line are cov-

ered with a metal liner, such as TaN/Ta

[31]

or TiN.

[32]

Typically, mass trans-

port along Cu grain boundaries is not dominant.

[10]

The fast diffusion paths

in Cu interconnects strongly depend on the materials and the fabrication

processes used, which vary for each laboratory.

[10–12, 33–37]

Fast diffusion

along the Cu/liner

[11, 12, 33–36]

or Cu/dielectric

[10, 27, 38]

interfaces has been

reported. The variation in the reported “fast paths” is probably due to sig-

nificant differences in the various integration processes, such as degas,

chemical-mechanical polishing (CMP) slurry, and precleaning steps

before depositing a capping layer on Cu. The fraction of the total Cu

atoms that are present at interfaces increases as the dimensions of the

interconnections are scaled down and cause further reduced chip lifetime in

every new generation. In addition, the Cu electromigration lifetime

distributions in dual-damascene lines have been found to have multiple

failure modes

[33–39]

and are further complicated by the reservoir effect in

structures of Cu line/Cu via/Cu line or Cu via to Cu line.

[38–40]

The reser-

voir effect occurs when the thin liner at the bottom of the via cannot

completely block Cu diffusion from a high electromigration-induced com-

pressive stress.

This chapter focuses on understanding the differences in test data as a

function of the test structure used, instead of the usual approach of present-

ing a functional fit to the change in resistance of lines to obtain

electromigration lifetime distribution. Furthermore, the relationship of elec-

tromigration lifetimes to (1) the barrier layer at the Cu line/via interface,

(2) the via size, and (3) the linewidth and diffusion paths is elucidated.

Correlations of electromigration lifetimes with void growth/sites and the

underlying diffusion mechanisms in Cu thin-film lines are emphasized. This

form of analysis is preferred because of an enhanced understanding of the

failure physics, which allows a much greater generalization of the experi-

mental findings and a more precise projection of IC Cu chip reliability.

406 DIFFUSION PROCESSES IN ADVANCED TECHNOLOGICAL MATERIALS

Chapter-09 11/29/04 6:50 PM Page 406

ELECTROMIGRATION IN CU THIN FILMS, HUETAL. 407

This chapter is divided into 14 sections. Section 9.2 reviews basic

interconnection integration. Section 9.3 describes the test structures

used in the experiments and discusses the experimental setup and fail-

ure analyses. Section 9.4 discusses the microstructure of the thin-film

interconnects. Section 9.5 describes the theoretical background infor-

mation of electromigration physics. Section 9.6 presents the line-

resistance change and void growth data. Section 9.7 discusses the

dominant diffusion paths for electromigration. Sections 9.8 and 9.9

present the lifetime distribution and current density dependencies,

respectively. Section 9.10 presents the relationship between lifetime

and metal linewidth. Section 9.11 presents the electromigration scaling

rules and lifetime prediction. Section 9.12 presents the short-length

effect in Cu interconnections. Section 9.13 discusses the reduction of

interface diffusion using surface coatings. Section 9.14 summarizes

the chapter.

9.2 Cu Interconnection Integration

On-chip Cu interconnections can be fabricated by two different

schemes.

[28]

The first approach is similar to conventional Al interconnect

processing and generally entails first patterning the metal lines, either by

dry etching, liftoff, or selective deposition, followed by dielectric deposi-

tion. Among dry-etching techniques, reactive ion etching (RIE)

[41]

and ion

milling

[28]

have been shown to pattern Cu lines. The second approach is to

pattern the dielectric level first, then fill metal into the patterned trenches

and holes, followed by CMPto remove the surface layer and planarize the

structure, leaving material in the holes and trenches. This approach is

known as damascene processing and has been commonly accepted by IC

manufacturers. Since the tested chips discussed in this chapter used both

approaches, we will briefly describe Cu interconnections fabricated by

liftoff, dry etching, and damascene processing.

For the liftoff process, a negative image of the metal line was pat-

terned in a resist layer. Then the metal was evaporated into the opening of

the resist. The metal on the resist was lifted off when the resist was

immersed in a resist solvent, leaving the desired metal lines on the sub-

strate. In the dry-etching process, the photoresist was patterned on the

Ta/Cu/Ta/SiNx multilayer structure. The photoresist was used as an etch-

ing hard mask to etch Ta/SiNx by RIE. Then the Cu lines were patterned

by argon and nitrogen plasma using photoresist, and silicon nitride/Ta

as the etch mask. Damascene processing was first used by IBM for

fabricating W-vias,

[42]

copper-polyimide,

[43, 44]

and Cu-SiO

[7, 45]

wiring

structures. For advanced Cu interconnection structures, Fig. 9.1(a)

Chapter-09 11/29/04 6:50 PM Page 407

through (d) and Fig. 9.1(e) through (h) depicts the single- and dual-

damascene sequences,

[46–48]

respectively. Atypical single-damascene level

is fabricated by the deposition of a planar dielectric stack, which is then

patterned and etched using standard lithographic and dry-etch techniques

to produce the desired wiring or via pattern. This is followed by physical

vapor deposition (PVD) of a metal liner, such as TaN/Ta, and a Cu seed,

then filled with Cu using an electroplating deposition technique.

[7]

In dual-

damascene processing, both the vias and the trenches are patterned in the

dielectric before depositing the metal. The excess metal in the field region

is then removed using a Cu CMP process, leaving planarized wiring and

vias imbedded in an insulator. Subsequent levels are fabricated by

repeated application of this process. In the damascene process, all wiring

levels are planar at every level, which typically results in enhanced wafer

yield over a nonplanar structure. Aseven-level damascene interconnection

408 DIFFUSION PROCESSES IN ADVANCED TECHNOLOGICAL MATERIALS

Figure 9.1 Process sequence used to fabricate a single-damascene [(a) through

(d)] and dual-damascene [(e) through (h)] Cu interconnect.

Chapter-09 11/29/04 6:50 PM Page 408

ELECTROMIGRATION IN CU THIN FILMS, HUETAL. 409

structure is shown in Fig. 9.2.

[9]

This structure demonstrates excellent

planarity and low contact resistance between the levels. Each level of

CuSiO

contains a dielectric trilayer of chemical vapor deposition

(CVD) SiN

SiO

SiN

The thin silicon nitride film coated on the Cu interconnection struc-

tures serves several functions: an adhesion layer between the levels, Cu

and H

O diffusion barrier, RIE mask for trench/via definition, RIE stop

(prevents exposure of lower Cu levels to O

RIE), and capping layer to

suppress Cu hillock formation and solvent absorption during subsequent

low-dielectric-constant (e) material cures.

[28]

However, in regions where

the high-dielectric-constant (e  7) SiN

remains between the dielectric

layers, the interline capacitance is increased. Other materials,

[49]

such as

SiC (e  5), SiC

(e  4.9), and a-SiC

(e  4.5), with lower dielec-

tric constant serving the same function as the silicon nitride have been

investigated in recent years.

9.3 Test Structure and Experiment

Figure 9.3(a) through (e) shows schematic diagrams of the test struc-

tures discussed in this chapter. Figure 9.3(a) is a Blech-type drift velocity

test structure

[50]

that consists of a series of Cu line segments on a continu-

ous Wunderlayer. Figure 9.3(b) through (d) and (e) shows three- and two-

level interconnect test structures, respectively. M0, M1, M2, and M3 are

the W local, the first Cu level, the second Cu level, and the third Cu level

interconnects. M1 connects to M0 and M2 through the CA and V1 vias,

respectively. M2 connects to M1 and M3 through the V1 and V2 vias,

respectively. In Fig. 9.3(b), the W M0 lines, W CA via, and Cu M1 were

fabricated by a single-damascene process. In Fig. 9.3(c) through (e), Cu

Figure 9.2 SEM cross-section image of an IC chip with seven levels of Cu

interconnects.

Chapter-09 11/29/04 6:50 PM Page 409

CA and Cu M1 were fabricated by a dual-damascene process. The upper

levels of V1M2 and V2M3 were also fabricated by dual-damascene

processes. The Cu interconnects were embedded in a SiN

SiO

dielectric or

amorphous a-SiC

SiLK™ dielectric. (SiLK semiconductor dielectric

is a trademark of the Dow Chemical Co.) The final Cu lines were passi-

vated with SiO

SiN

, and the Al(Cu) metallization was used to coat the

bonding pads. However, some samples with no passivation on top of Cu

lines were also studied.

The Cu line/via microstructure was analyzed by both focused ion

beam (FIB) microscopy and scanning transmission electron microscopy

(STEM). The thickness and width of the metal lines and vias were

measured from either FIB, scanning electron microscopy (SEM), or

TEM images. Void growth and extrusion of the tested lines were also

examined by FIB and SEM on cross sections prepared by FIB. Other

investigators have used transmission X-ray microscopy

[51, 52]

or high-

voltage (120 keV) SEM

[53]

to observe void size and growth. A dc cur-

rent was applied to the test lines. Failure time, t, was determined by

410 DIFFUSION PROCESSES IN ADVANCED TECHNOLOGICAL MATERIALS

Figure 9.3 Test structures discussed in this chapter. (a) Blech-type drift velocity

setup on W; (b) and (c) three-level-metal structure of M0/CA/M1/V1/M2; (d) three-

level-metal structure of M1/V1/M2/V2/M3; (e) two-level-metal structure M0/CA/M1.

Chapter-09 11/29/04 6:50 PM Page 410

ELECTROMIGRATION IN CU THIN FILMS, HUETAL. 411

the time to increase the line resistance significantly from the initial

value R

by 2%, ∆RR

 2%. The failure time distribution was ana-

lyzed as a log-normal

[22]

or a multi-log-normal distribution, depending

on the test structures used.

9.4 Microstructure

Cu microstructure is an important factor in determining the diffusion

and mass transport rate. The grain size distribution, crystallographic tex-

ture, surface plane orientation, and impurity distribution are all related to

Cu diffusivity. The diffusion will determine the electromigration drift

velocity, and variation of local microstructure can cause an electromigra-

tion flux divergence. The texture of lines can be controlled by the texture

of the underlying Ti and TiN,

[32]

TiW,

[54]

Ta,

[32, 54]

or TiN,

[54]

and a highly

111 textured Cu showed improved electromigration resistance in a

one-level line structure. The grain distribution of PVD Cu films has been

reported previously and is generally found to be bimodal with a signifi-

cant twinned grain volume fraction.

[55]

Texture components of 111,

200, random, 220, and 511 in PVD Cu have been

reported.

[55, 56]

Grain growth, texture, and microstructure of electroplated

Cu films have gained much attention in recent years because the electro-

plating technique has been widely chosen as the main process for Cu filling

in damascene lines. This is because the electroplating process of filling

Cu in trenches/vias from the bottom up is far superior to the other

processes. Abimodal grain size distribution, considerable random texture

components, and a high degree of twinning have been found in electro-

plated Cu thin films.

[57]

In Cu damascene lines, the 111 texture

decreases as the linewidth decreases from 1 to 0.3 mm, and the twinned

grain volume fraction increases after annealing.

[29]

Further, it is known

that texture in electroplated films is sensitive to a large number of depo-

sition parameters, such as liner/Cu seed-layer microstructure, electro-

plating current density, and bath chemistry.

[58]

Figure 9.4(a) through (d)

shows plan-view FIB images of 3-, 2-, 0.8-, and 0.18-mm-wide electro-

plated Cu lines, respectively, taken at an ion beam angle of 10 degrees.

Figure 9.4(e) is a cross-section view FIB image of a 0.18-mm-wide electro-

plated Cu dual-damascene line, taken at an ion beam angle of 45 degrees.

In these images, large grains and twins are seen. The interfacial energies

of a Cu twin boundary and a normal grain boundary are reported to be

44 erg/cm

2[59]

and 650 erg/cm

[60]

respectively. The small interfacial

energy at twin boundaries and reasonable match between twin and parent

lattices across a twin plane imply that Cu diffusion along a twin bound-

ary should be close to Cu bulk diffusion. Thus, twin boundaries are not

Chapter-09 11/29/04 6:50 PM Page 411