Ghodssi R., Lin P., MEMS Materials and Processes Handbook

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884 A.G. Darrin and R. Osiander

Optical MEMS packaging differs from traditional semiconductor/

microelectronics packaging in several ways. Optical MEMS packages often

are required to provide optical and electrical access, hermeticity, mechanical

strength, dimensional stability and long-term reliability. Hermetic optical access

necessitates t he use of metalized or glass sealed and anti-reﬂection coated windows.

In addition, the ever-increasing electrical I/O count has prompted the use of higher

density substrate/package technologies [2]. The reason for hermetic packaging is to

ensure the long-term reliability of the expensive, state-of-the-art optical systems.

Traditional FR-4 laminate-based technology is eliminated and packaging choices

are restricted to mostly ceramic-based technologies such as high temperature

co-ﬁred ceramic (HTCC), low temperature co-ﬁred ceramic (LTCC), and thin-ﬁlm

ceramic technologies. Since frames and windows are ﬁrst sealed together, their

mechanical properties, especially their coefﬁcient of thermal expansion (CTE),

have to be well matched to those of mating package materials. These requirements

limit the material choices; frames are often made of Kovar

, and windows are

often made of sapphire. Some windows are wedge-shaped to avoid Fabry-Perot

effects. In general, optical MEMS packages are mounted to metal housings to

maintain critical optical alignments. They have to be rigid and dimensionally

stable over all operating temperatures to have optimized and repeatable optical

performance. Any misalignments between the optics and the MEMS devices can

easily translate into losses that may result in out of tolerance conditions that degrade

system performance.

12.1.4.3 Microﬂuidic Interface

For microﬂuidic systems, the diverse range of applications often dictates custom

designs in packaging. A microﬂuidic system typically integrates both ﬂuidic and

electrical components while also requiring mechanical integrity. The technical chal-

lenges with integrating micro-scale devices into macro-scale ﬂuidic sources are:

(1) obvious dimensional incompatibilities as the introduction of ﬂuid samples and

reagents into microﬂuidic devices in precise quantities from the macroscopic world

creates a grand challenge; and (2) stability issues (including mechanical such as

pressure and hermeticity) in the micro-scale caused by physical stresses arising from

macro-scale ﬂuidic connections. Apart from the challenges associated with chip-to-

world ﬂuidic interconnections, other major problems with packaging of microﬂuidic

devices arise from the leakages of ﬂuids. Fluidic leakages occur due to two r easons:

(1) failure to handle the ﬂuidic pressures from interconnect components; and (2) the

use of an incorrect clamping force for proper sealing between various layers of the

device. To avoid such issues, epoxy has been utilized to permanently attach ﬂuidic

tubing in many microﬂuidic packages, while a sealed connection among microﬂu-

idic interconnects has been achieved by interlinking the machined top part of the

ﬂuidic tubing to an O-ring, a custom made ring, or a coupler. As there are diverse

structures and applications of microﬂuidic devices, it is difﬁcult to develop a generic

ﬂuidic interconnect and packaging system [3].

12 MEMS Packaging Materials 885

12.1.4.4 Environmental Interface

Unique to many MEMS applications is the need for environmental contact, and

in some cases, physical interaction with the surroundings. Pressure sensors, opti-

cal devices, and nozzles that typically require direct contact between the MEMS

and the environment are often “non-capped” components. In such systems, a sealed

lid/cap is not optimal, and instead, an unsealed gel lid/cap may be used to protect

interconnect wires and other MEMS component parts. As an example, a typical

pressure sensor detects changes in strain signals as pressure is applied on two sides

of a diaphragm. On one side of the diaphragm is a ﬁxed and sealed reference vol-

ume, while on the opposite side, environmental pressure is sensed by a strain gauge

differential pressure sensor that measures diaphragm deﬂection.

12.2 Package Selection

Material selection is an important step in packaging and must be addressed from

the early stages of development as it can affect manufacturing. When packaging

microcircuits, a chip can be placed in any one of several hermetic packages. For

example, it is common to procure a chip in any of a number of off-the-shelf ceramic

packages, such as leadless chip carriers (LCC), dual-in-line packages, ﬂat packs,

quad ﬂat packs, and quad chip carriers, each with various lead or leadless conﬁgura-

tions. Although these styles are also common for MEMS components, these ceramic

package conﬁgurations are sometimes not appropriate for wafer technologies that

are geared for unique applications. As a rule, package choices for MEMS are more

restrictive t han for microcircuits because of the many unique functions offered by

MEMS devices. Figure 12.2 shows a typical ceramic MEMS sensor package.

Material Compatibility with the Component and Application. Materials are cho-

sen based on chemical, mechanical, electrical, and optical compatibilities. The

Fig. 12.2 Ceramic sensor

package for MEMS (courtesy

Kyocera Corporation)

886 A.G. Darrin and R. Osiander

performance of a complex system composed of packaging, MEMS, and attach

materials can be adversely affected by either manufacturing or service conditions.

Some difﬁcult packaging challenges have been encountered with optical MEMS in

particular.

Cleanliness of the Process. Contamination during assembly and joining, as well

as from aging, could adversely affect the device, especially those devices with

open and exposed moving components. Thus, control of particulate matter dur-

ing the attachment, joining, and curing processes should be carefully chosen during

manufacturing to avoid contamination.

Single Level or Die Stacking. A growing trend to deliver more functional per-

formance per square centimeter of a packaged area poses a great challenge to

manufacturing. To meet these demands, die are often stacked on top of one another

to save area. Stacking is achieved in a single pass through automated placement of

a die proceeded by application of an adhesive.

Flip Chip or Face Up/Wire Bond. The choice between ﬂip chip and face up/wire

bonding affects many of the areas discussed above and must be considered carefully

for cost and reliability [4].

Examples of material properties for various packaging materials are found in

Table 12.2; metal and ceramic properties are found in their respective sections.

12.2.1 Metal

Metal packages have commonly been used for microwave multi-chip modules and

hybrid circuits as they provide both good thermal dissipation and electromagnetic

shielding in addition to isolating the contents from harmful contact with surround-

ings. These packages, developed for semiconductors, can have a large internal

volume while maintaining mechanical reliability. Metal package materials are dic-

tated primarily by integrity of the glass or ceramic feedthroughs, restricting choices

to low expansion metals that minimize thermal expansion mismatches. Properties

of some typical materials used with metal packages is given in Table 12.3 [5].

Materials such as CuW (10/90), Silvar-K



, CuMo (15/85), and CuW (15/85)

have superior thermal conductivities and higher CTE values than silicon, making

them popular choices for shims between the silicon and the package. Materials

like Kovar

and other high nickel alloys are used because their t hermal expansion

properties are a close match to ceramics and sealing glasses. Packages are usually

ﬁnish plated with nickel, silver, or gold.

Corrosion or reactivity, through trapped or absorbed gases or moisture, becomes

a concern with metal packages. Such effects are usually eliminated by baking prior

to ﬁnal hermetic sealing, which is done by either welding or solder sealing a lid to

the base. As a rule, assembly process temperatures are decreased with each assembly

step to minimize manufacturing stresses.

Hermeticity in metal packages is affected by the quality of both the package lid

seal and the feedthroughs. Feedthroughs using glass to metal or ceramic (HTCC).

High temperature coﬁred ceramic package (HTCC) is a multilayered, sealed

12 MEMS Packaging Materials 887

Table 12.2 Properties of non metal/ceramic packaging materials

Silicone Polyurethane Acrylic

Epoxy,

silicone

Epoxy,

Novolak

Epoxy

bisphenol A

Epoxy,

electrically

conductive Polyimide

Epoxy

phenolic

Volume resistivity

( m)

–10

0.3×10

7×10

–10

Dielectric constant

@1MHz

2.9–4.0 5.9–8.5 – 3.4–3.6 3.2–3.8 3.4

Dielectric strength

(kV/mm)

8–27.6 12.9–23.6 – – – 15.8

Dissipation

factor

@1MHz

0.001–0.002 0.005–0.06 – 0.016 0.013–0.024 – 0.32

Tensile strength MPa 10.5 urethane

5.5–55

12.4–13.8 55.0–82.7 43–85 3.4–34 – –

Shear

strength

MPa

urethane

15.5

– 12.7 26.2 – – 16.5

Modulus of elasticity

GPa

2.21 – 0.069–10.3 – 2.76–3.45 2.7–3.5 3.0

Elongation (%) 100–800 urethane

250–800

100–400 – 2–5 4.40–12.0 —

Speciﬁc gravity 1.06–1.2 urethane

1.1–1.6

1.09 1.2 1.15

Hardness 20–90A urethane

10A–800

40–90A 106RM

Thermal conductivity

(W/m

◦

6.4–7.5 1.9–4.6 13–26 0.17–1.5 0.2 25.0–74.7

CTE

(ppm/

◦

262–300 90–450 60–80 40–50 33

Heat Capacity (J/kg-

◦

C) – – 1674–2003

Max Temperature (

◦

C) 260 65.6 93.3 260 87.8

A=Shore; D=Shore; RM=Rockwell M

888 A.G. Darrin and R. Osiander

Table 12.3 Common materials used in metal packages

Material CTE (ppm/

◦

Thermal conductivity

(TC)(W/m

K) Density (g/cc)

CuW/15–85 7.0 180 16.40

AlSiC 6.7 180 3.00

CuMo/15–85 6.6 184 10.00

Silvar-K

7.0 110 8.80

CuW/10–90 6.5 209 17.00

BeO 6.4 250 2.78

Kovar

5.9 14 8.42

Molybdenum 5.1 140 10.25

package created using layers of ceramic tape with thicknesses ranging from 5 to

25 mm, which are laminated together. The coﬁred ceramic packages’ tape layers,

consisting of 92% aluminum oxide ceramic, tungsten and moly-manganese, have

metalized circuit patterns. Conductive vias pierce the tape layers, forming electri-

cal interconnects between circuits. The ceramic packages’ tape layers are laminated

under pressure and the ceramic and metallization are co-sintered at 1600

◦

C, creat-

ing a monolithic structure with a three dimensional wiring system to which metal

seals can be applied. A challenge for ceramic feedthroughs is the conductor that is

generally metalized must seal with the ceramic. Complete wetting of the conduct-

ing pin to the ceramic during metallization must be achieved. Otherwise, incomplete

wetting may result in failure during thermal cycle testing.

12.2.2 Ceramic

Ceramic packages have several features that make them especially useful for MEMS

and microelectronic packaging. Ceramic packages can be made hermetic and

can withstand harsh operating conditions. With high modulus of elasticity and

ﬂexural strength, ceramics can be a rigid base for devices that require accurate sens-

ing. Ceramics can have multiple layers of signal distribution lines and can have

multiple mounting orientations. A single package can be designed to be mounted

both horizontally and vertically. Multilayer ceramic packages also allow reduced

size and total system cost, especially over metal-walled packages, by integrating

multiple MEMS and/or other components in a single, hermetic package through the

use of cavities and internal signal routing. Figure 12.3 shows a typical multilayer

package cross section.

Lastly, ceramics have high thermal conductivity and low coefﬁcient of thermal

expansion, which minimizes the stress placed on the MEMS device over a large

operating ranges and also efﬁciently transfers heat away from the device without

the use of thermal vias or heat spreaders. These multilayer packages also offer sig-

niﬁcant size and mass reduction over metal-walled packages. Most of this advantage

12 MEMS Packaging Materials 889

Fig. 12.3 Typical structure for a multilayer ceramic package (Reprinted with permission of the

Kyocera Corp)

is derived by the ability to use three dimensions instead of two for interconnect lines.

Table 12.4 gives the material properties for two common ceramic packages [6].

Ceramic packages have ﬂexural strengths between 400 and 620 MPa, thermal

conductivities between 14 and 21 W/mK, and thermal coefﬁcients of expansion

ranging between 6.9 and 7.2 ppm/

◦

C. The ceramic package can provide a stable

platform for sensor mounting and yet be sensitive to external stresses. Furthermore,

Table 12.4 Ceramic package materials properties (courtesy the Kyocera Corporation) material

characteristics

Items Units Alumina

A440 A443

Bulk density 3.6 3.7

Electrical

Dielectric constant (1 MHz) – 9.8 9.6

Dissipation factor (1 MHz) (1 × 10

−4

)24 5

Volume resistivity (25

◦

C) m10

>10

Thermal

CTE (RT −400

◦

C) (ppm/K) 7.1 6.9

Thermal conductivity W/mK 14 18

Speciﬁc heat (1 × 10

J/KgK) 0.77 0.77

Mechanical

Flexural strength MPa 400 460

Young’s modulus of elasticity GPa 310 310

Conductor material – W. Mo W. Mo

Feature – High Strength

Color of ceramics – Brown/Black Brown/Black

Note: Material characteristics mentioned above are typical values. These values may change upon

further improvement or modiﬁcation of these materials and processes

890 A.G. Darrin and R. Osiander

capable of meeting a maximum leak rate requirement of 1 ×10

−8

atm cc

/s He (at

1 atm), these packages can also offer a hermetic seal for sensors that are degraded

by atmospheric contact. To meet the demands of miniaturization, ceramic pack-

ages can provide multiple die packaging arrangements; internal cavity structures

and lines/spaces; footprints as small as 3 mm × 3 mm; and package proﬁles

less than 1 mm in height [7]. Table 12.5 shows properties of typical package

materials [7].

Table 12.5 Comparison of typical package materials used in ceramic packages

Alumina

(HTCC)

Glass ceramics

(LTCC) Mold resin

Glass epoxy

(FR-4)

Flexural strength 400–620 MPa 170–400 MPa 170 MPa 550 MPa

Elastic modulus 260–315 GPa 75–190 GPa 19 GPa 25 GPa

Coefﬁcient of thermal

expansion

6.9–7.2 ppm/

◦

C 5.4–8.4 ppm/

◦

C 12 ppm/

◦

C 12–15 ppm/

◦

Thermal conductivity 14–21 W/m

K 1.5–3.6 W/m

K 0.8 W/m

K 0.2 W/m

Dielectric constant

(@ 1 MHz)

9.0–9.8 4.9–7.8 4.2 4.8

Glass transition

temperature

N/A N/A 130

◦

C 170

◦

HTCC is comprised of alumina (90–92%), but it can easily be confused with post-ﬁred alumina

blanks. Post-ﬁred alumina has application in electronic packaging, but for thick-ﬁlm and thin-ﬁlm

products, and post-ﬁred alumina typically ranges at 96–99.6% purity

Co-ﬁred ceramic packages are constructed from thin pliable ﬁlms of ceramic

material in the “green” or unﬁred state. Metal lines are deposited on the surface

using a screen printed thick-ﬁlm process; “via” holes to connect the layers are drilled

or punched in the “green” state. The unﬁred pieces are stacked and aligned using

registration holes before they are laminated together and ﬁred at high temperatures;

plating adds the proper metal surfaces. The MEMS or other components are then

attached using epoxies or solders; wire bond connections are made using the same

methods as for metal packages.

Normal shrinkage during the ﬁring step of green-state ceramics may induce

design dependent stress in the ﬁnished package. Since the unﬁred metals and green

ceramics shrink at different rates during ﬁring, the number and position of via holes

and the line direction and metal fraction of each layer has to be balanced; also,

because ceramic-to-metal adhesion is weaker than ceramic-to-ceramic adhesion,

metal grids rather than solid planes are used for power/ground planes and shield-

ing. For conventional multilayer ceramics, only refractory (W or Mo) metals can

be used because of ceramic ﬁring temperatures (approx. 1600

◦

C). Ag, AgPd, Au,

and AuPt conductors can be used with low temperature co-ﬁred ceramic (LTCC)

packages that ﬁre at thick ﬁlm temperatures (approx 850

◦

C).

12 MEMS Packaging Materials 891

12.2.3 Plastic

Although plastics were used earlier for discrete transistors, plastic packages became

mainstream products with the introduction of dual-in-line packages (DIP). Such

packages remained as the most common commercial products throughout the inte-

grated circuit revolution of the late 20th century. Low manufacturing costs of such

materials have them widely used by the electronics industry and other applications.

However, questions regarding their use in high reliability applications have been

raised. Plastic packages are permeable to water vapor and often do not consistently

provide the robust seals required in high reliability applications. Products are also

susceptible to cracking (“popcorning”) in humid environments and during PWB sol-

dering or rapid temperature cycling. For these reasons, plastic packages have been

slow to gain wide acceptance in aerospace applications.

However, some newer semiconductor designs that are only available in

plastic packages are beginning to be ﬂown in space applications. Programs

such as Commercial off the Shelf (COTS), which include Plastic Encapsulated

Microelectronics (PEMs), are gaining acceptance. For example, suitable PEMs were

used for The Applied Physics Laboratory’s Thermosphere-Ionosphere-Mesosphere

Energetics and Dynamics (TIMED) program. The size, cost, and weight constraints

of the TIMED mission were achieved only with commercially available devices [8].

Since MEMS devices have moving parts, direct contact with encapsulants is not

an option unless specially capped MEMS chips are used. In the plastic package,

the chip is typically connected to a metal lead frame (MLF) by wire bonding fol-

lowed by transfer overmolding with epoxy molding compound (EMC). Molding

compound is a mix of solid epoxy resins, hardeners, ﬁllers, and additives that is

easily liqueﬁed by modest heating to allow the melt to be forced into a mold that

holds the lead frame assembly. The heated thermoset EMC polymerizes to a per-

manent solid and comes into direct contact with the chip, wire bonds, and MLF.

The Ball Grid Array (BGA) style package can use a similar overmolding method

but an organic (plastic) substrate typically is used in place of the MLF. However,

overmolding of capped MEMS can stress-degrade their performance because of

epoxy shrinkage around the device. Some capped MEMS products have moved

away from thermoset overmolding to thermoplastic cavity packages [9]. Table 12.6

shows typical thermoplastics used in packaging [9].

Table 12.6 Typical thermoplastics used in packaging

Plastic Water abs. (%)

Melting point

(

◦

Flammability

(Class UL94)

CTE/30% glass

(ppm)

LCP – Liquid crystal

polymer

0.02–0.10 280–352 V-O 0–12

PEEK –

Polyetheretherketone

0.15 340 V-O 16

PPA – Polyphthalamide 0.15–0.29 310–332 H-B V-O 22–40

PPS – Polyphenylene

sulﬁde

0.01–0.04 280 V-O 19–27

892 A.G. Darrin and R. Osiander

12.2.4 Array Packaging Materials/Wafer Level Packaging

Wafer Level Packaging (WLP) involves bonding of silicon structures. Such pro-

cesses usually entail capping of fragile structures to ensure proper isolation from

the surrounding environment. Processes vary by applications, and custom solutions

are dictated by MEMS chips. Concerns for the damages that arise during assem-

bly operations of wafer level packaging need to be addressed. Fabrication steps

include dicing, pick-and-place die mounting, wire bonding, soldering, and sealing.

Structural support and protection are provided by the use of a capping technique.

Two approaches for encapsulation are currently in use: wafer-to-wafer bonding,

and die-to-wafer bonding. The general idea of wafer-to-wafer bonding is to cap

the wafer containing the MEMS structures with a separate, micromachined wafer

in which a small cavity is made or a standoff ring is present. Wafer bonding uses

anodic, fusion, or glass-frit sealing which is discussed in Section 12.4.2. For die-to-

wafer bonding, preprocessed and diced caps are placed on the wafer by means of a

ﬂip chip bonder. With larger die, the approach offers economical advantages over

wafer-to-wafer bonding; the longer bonding process time for mounting individual

caps is balanced by making the wire bond pads readily accessible. This technique

can be used for low-temperature sealing materials, including solder seals with her-

meticity below 10

−11

mbar 1/s (1 (torr/1)/s = 1.31578947 × 10

−6

(atm/cc)/s). It

can also be used for thin caps [10].

12.2.5 Custom Packaging

Most packaging methods discussed in this chapter must be customized for speciﬁc

applications. WLP is evolving to applications for 3D interconnect in addition to

capping, shifting its application forward in the manufacturing process. Through-

silicon vias are being used to connect MEMS, CMOS image sensors and memory

devices. The newest requirement for wafer bonding arises from 3D integrated

bonding. Two emerging packaging applications involve CMOS image sensors with

backside illumination and DRAM stacking utilizing polymer adhesive bonding or

direct oxide bonding. Integration of metallic bonding techniques, such as Cu dif-

fusion, for next-generation 3D CMOS is also currently advancing rapidly. Recent

packaging advances include the integration of silicon through implementation of

system-in-package (SiPs) and 3D stacking of both dies and packages [11].

12.2.6 Silicon Encapsulation

As a wafer packaging approach, sputtered silicon encapsulation is viable for MEMS

devices requiring isolation. Devices that do not require interaction with the sur-

roundings to function, such as accelerometers, RF switches, inductors, and ﬁlters

can be fully encapsulated at the wafer level after fabrication. In one example, a

MEMSTech 50 g capacitive accelerometer was used to demonstrate a sputtered

12 MEMS Packaging Materials 893

encapsulation technique. Encapsulation with a very uniform surface proﬁle was

achieved using spin-on glass (SOG) as a sacriﬁcial layer, SU-8 as a base layer, RF

sputtered silicon as the main structural layer, eutectic gold-silicon as a seal layer,

and liquid crystal polymer (LCP) as the outer encapsulant layer. SEM inspection

and capacitance tests indicated that the movable elements were released after encap-

sulation [12]. SU-8 is a commonly used epoxy-based negative photoresist. It is a

very viscous polymer that can be spun or spread over a thickness ranging from 0.5

micrometer up to 2 mm and still be processed with standard contact lithography.

SU-8 was originally developed as a photoresist for the microelectronics industry

to provide a high resolution mask for fabrication of semiconductor devices. SU-8

is frequently used in the fabrication of microﬂuidics and MEMS parts. It is also a

biocompatible material and is often used in bio-MEMS. Other examples include the

use of epitaxially deposited polysilicon as an encapsulation structure for piezoresis-

tive accelerometers [13]; plasma enhanced chemical vapor deposition of polysilicon

[14]; and the use of permeable polysilicon to fabricate a vacuum shell over movable

elements of a MEMS resonator [15]; and the use of a silicon cap bonded with glass

frit over an accelerometer as shown in the case studies in Section 12.11.1. With such

methods, use of an outer encapsulant should be considered to strengthen the i nitial

encapsulation structure to withstand the subsequent transfer molding process, and

care should be taken to assure that using any additional glob top does not further

induce stress, especially during the hardening and curing steps.

12.2.7 Glass Encapsulation

Glass is predominantly used in capping operations and considerations in the use

of glass include the matching of the coefﬁcients of thermal expansion. Glass has

high strength, especially in compression applications, and good electrical properties.

Localized stress concentrations are usually related to the base material imperfec-

tions. The use of a glass cap process is extremely ﬂexible and allows MEMS devices

with different designs to be packaged on one chip or wafer. In contrast to silicon

(ε

= 11.9) as packaging material, a glass cap (ε

= 4.6) has a low dielectric con-

stant and usually has a negligible inﬂuence on the RF performance. Furthermore,

glass is transparent, allowing optical control of the packaged device. A typical glass

cap consists of a 300 μm thick glass plate diced from a wafer, and a cavity 100 μm

in depth is precisely milled into its center to accommodate the MEMS component.

The design of the glass caps is extremely ﬂexible, since almost any shape and size

can be fabricated. It is possible to cover a single chip or even a whole wafer with

one single glass cap [16]. An example of an optically encased window is shown at

the end of this chapter in Section 12.11.1.

12.3 Lids and Lid Seals

There are ﬁve major methods of sealing packages: seam or projection welding, high

temperature (AuSn) or low temperature soldering, low temperature glass sealing,