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874 S.J. Cunningham a nd M. Kupnik

18. K.A. Reinhardt, W. Kern: Handbook of Silicon Wafer Cleaning Technology, 2nd ed (William

Andrew, Norwich, NY, 2008)

19. Z. Liu et al.: Micromechanism fabrication using silicon fusion bonding, J. Robot. Comput.

Integr. Manuf. 131–137 (2001)

20. G.-L. Sun et al.: Cool plasma activated surface in silicon wafer direct bonding technology,

J. Phys. 9, 79–82 (1988)

21. J. Köhler et al.: Silicon fusion bond interfaces resilient to wet anisotropic etchants,

J. Micromech. Microeng. 11, 359–363 (2001)

22. A.F. Sarioglu, O. Solgaard: Cantilevers with integrated sensor for time-resolved force mea-

surement in tapping-mode atomic force microscopy, Appl. Phys. Lett. 93, 023114-1-3

(2008)

23. K.K. Chan et al.: Low temperature fusion bonding with high surface energy using a wet

chemical treatment, US Patent, US 7566631 B2 (2009)

24. Y.L. Chao et al.: Ammonium hydroxide effect on low-temperature wafer bonding energy

enhancement, J. Electrochem. Soc. 8(3), G74–G77 (2005)

25. T. Rogers, N. Aitken: Low temperature bonding using in-situ radical activation, ECS Trans.

16, 507–516 (2008)

26. K.Y. Byun et al.: Effect of free radical activation for low temperature Si to Si wafer bonding,

J. Electrochem. Soc. 157(1), 109–112 (2010)

27. K.Y. Byun et al.: Low temperature germanium to silicon direct wafer bonding using free

radical exposure, Appl. Phys. Lett. 96, 102110-1-3 (2010)

28. C. Harendt et al.: Wafer fusion bonding and its application to silicon-on-insulator fabrication,

J. Micromech. Microeng. 1(3), 145–151 (1991)

29. Y. Bäcklund et al.: A suggested mechanism for silicon direct bonding from studying

hydrophilic and hydrophobic surfaces, J. Micromech. Microeng. 2(3), 158–160 (1992)

30. G. Wallis, D.I. Pomerantz: Field-assisted glass-metal sealing, J. Appl. Phys. 40, 3946–3949

(1969)

31. K.B. Albaugh: Electrode phenomena during anodic bonding of silicon to sodium borosilicate

glass, J. Electrochem. Soc. 138, 3089–3094 (1991)

32. K.B. Albaugh, D.H. Rasmussen: Rate processes during anodic bonding, J. Am. Ceram. Soc.

75, 2644–2648 (1992)

33. S.J. Cunningham, D.R. DeReus, J.W. Borninski: An Electro-mechanical Analysis of the

Anodic Bond Process for Microelectromechanical Systems, In Semiconductor wafer bond-

ing: Science, Tech., and App., Proceedings of the Electrochemical Society, 196th Meeting,

Oct 17–22, pp. 326–337 (Honolulu, HI, 1999)

34. S. Cunningham, S. Tatic-Lucic, J. Carper, J. Lindsey, L. Spangler: A High Aspect

Ratio Accelerometer Fabricated Using Anodic Bonding, Dissolved Wafer, and Deep RIE

Processes, Transducers 99, Sendai, Japan, pp. 1522–1525 (1999)

35. L. Spangler, C. Kemp: ISAAC: Integrated Silicon Automotive Accelerometer, Transducers

95 and Eurosensors IX, June, 25–29, pp. 585–588 (Stockholm, Sweden, 1995)

36. L. Spangler, C. Kemp: ISAAC: Integrated silicon automotive accelerometer, Sens. Actuators

A Phys. 54, 523–529 (1996)

37. M.J. Wild, A. Gillner, R. Poprawe: Locally selective bonding of silicon and glass with laser,

Sens. Actuators A Phys. 93, 63–69 (2001)

38. C.H. Tsau, S.M. Spearing, M.A. Schmidt: Fabrication of wafer-level thermocompression

bonds, J. Microelectromech. Syst. 11, 641–647 (2002)

39. R.F. Wolffenbuttel, K.D. Wise: Low-temperature silicon wafer-to-wafer bonding using gold

at eutectic temperature, Sens. Actuators A 43, 223–229 (1994)

40. F. Niklaus, P. Enoksson, P. Griss, E. Kälvesten, G. Stemme: Low-temperature wafer-level

transfer bonding, J. Microelectromech. Syst. 10, 525–531 (2001)

41. F. Niklaus, P. Enoksson, P. Griss, E. Kälvesten, G. Stemme: Low-temperature full wafer

adhesive bonding, J. Micromech. Microeng. 11, 100–107 (2001)

11 Wafer Bonding 875

42. F. Niklaus, P. Enoksson, E. Kälvesten, G. Stemme: Void-free full wafer adhesive bonding,

IEEE MEMS 2000, The Thirteenth Annual Int. Conf. on Micro Electro Mechanical Systems,

23–27 June 2000, pp. 247–252 (Miyazaki, Japan, 2000)

43. G. Roelkens, J. Brouckaert, D. Van Thourhout, R. Baets, R. Nötzel, M. Smit: Adhesive

bonding of InP/InGaAsP dies to processed silicon-on-insulator wafers using DVS-bis-

benzocyclobutene, J. Electrochem. Soc. 153, G1015–G1019 (2006)

44. R. Puligadda, S. Pillalamarri, W. Hong, C. Brubaker, M. Wimplinger, S. Pargfrieder: High

performance temporary adhesives for wafer bonding applications, Mater. Res. Soc. Symp.

Proc. vol. 970, pp. 239 (2007)

45. H.S. Kim, K. Najaﬁ: Wafer Bonding Using Parylene and Wafer-Level Transfer of Free-

Standing Parylene Membranes, Transducers 03 12th International Conference on Solid State

Sensors, Actuators, and Microsystems, Boston, MA, pp. 790–793 (2003)

46. H. Kim, K. Najaﬁ: Characterization of low-temperature wafer bonding using thin-ﬁlm

parylene, J. Microelectromech. Syst. 14, 1347–1355 (2005)

47. H.-S. Noh, K.-S. Moon, A. Cannon, P.J. Hesketh, C.P. Wong: Wafer bonding using

microwave heating of parylene intermediate layers, J. Micromech. Microeng. 14, 625–631

(2004)

48. I. Christiaens, G. Roelkens, K. De Mesel, D. Van Thourhout, R. Baets: Thin-ﬁlm devices

fabricated with benzocyclobutene adhesive wafer bonding, J. Lightwave Technol. 23,

517–522 (2005)

49. A. Jourdain, X. Rottenberg, G. Carchon, H.A.C. Tilmans: Optimization of 0-level packag-

ing for RF-MEMS devices, Transducers 03, 12th International Conference on Solid State

Sensors, Actuators and Microsystems, Boston, MA, pp. 1915–1918 (2003)

50. C.T. Pan: Selective low temperature microcap packaging technique through ﬂip chip and

wafer level alignment, J. Micromech. Microeng. 14, 522–529 (2004)

51. D. Pasquariello, K. Hjort: Plasma-assisted InP-to-Si low temperature wafer bonding, IEEE

J. Quantum Electron. 8, 118–131 (2002)

52. C.B. Eom, L. Huang, R.A. Rao, Q.-Y. Tong, U. Gösele: Fabrication of double sided

YBa

thin ﬁlms on 2 inch diameter LaAlO3 wafers by direct wafer bonding, IEEE

Trans. Appl. Supercond. 7, 1244–1248 (1997)

53. J. Jasinski, Z. Liliental-Weber, S. Estrada, E. Hu: Microstructure of GaAs/GaN interfaces

produced by direct fusion bonding, Appl. Phys. Lett. 81, 3152–3154 (2002)

54. P. Kopperschmidt, Senz, St. Kästner, D. Hesse, U. Gösele: Wafer bonding of gallium

arsenide on sapphire, Appl. Phys. A64, 533–537 (1997)

55. B.E. Roberds, K.D. Choquette, K.M. Geib, S.H. Kravitz, R.D. Twesten, S.N. Farrens:

Wafer Bonding of GaAs, InP, and Si Annealed Without Hydrogen for Advanced Device

Technologies, Proceedings of the Electrochemical Society, Paris, France (1997)

56. P. Kopperschmidt, G. Kästner, D. Hesse, N.D. Zakharov, U. Gösele: High bond energy and

thermomechanical stress in silicon on sapphire wafer bonding, Appl. Phys. Lett. 70(22),

2972–2974 (1997)

57. G. Taraschi, T.A. Langdo, M.T. Currie, E.A. Fitzgerald: Relaxed SiGe-on-insulator fabri-

cated via wafer bonding and etch back, J. Vac. Sci. Technol. B 20, 725–727 (2002)

58. G. Taraschi, A.J. Pitera, L.M. McGill, Z.-Y. Cheng, M.L. Lee, T.A. Langdo, E.A. Fitzgerald:

Ultrathin strained Si-on-insulator and SiGe-on-insulator created using low temperature

wafer bonding and metastable stop layers, J. Electrochem. Soc. 151, G47–G56 (2004)

59. G. Taraschi, A.J. Pitera, E.A. Fitzgerald: Strained Si, SiGe, and Ge on-insulator: Review of

wafer bonding fabrication techniques, Solid-State Electron. 48, 1297–1305 (2004)

60. T. Akatsu, A. Plößl, H. Stenzel, U. Gösele: GaAs wafer bonding by atomic hydrogen surface

cleaning, J. Appl. Phys. 86, 7146–7150 (1999)

61. S. Farrens, P. Lindner, V. Dragoi, G. Mittendorfer: Integrating MEMS devices using low-

temperature wafer bonding, Solid State Technol. 49(2), (2006)

876 S.J. Cunningham a nd M. Kupnik

62. H. Lin, A.J. Walton, C.C. Dunare, J.T.M. Stevenson, A.M. Gundlach, S. Smith, A.S.

Bunting: Test structures for the characterization of MEMS and CMOS integration technol-

ogy, IEEE Trans. Semicond. Manuf. 21, 140–147 (2008)

63. L. Parameswaran, C. Hsu, M.A. Schmidt: A merged MEMS-CMOS process using silicon

wafer bonding, IEEE IEDM, Washington, DC, pp. 613–616 (1995)

64. S. Sedkey, A. Witvrouw, H. Bender, K. Baert: Experimental determination of the maxi-

mum post-process annealing temperature for standard CMOS wafers, IEEE Trans. Electron

Devices 48, 377–385 (2001)

65. S. Van der Groen, M. Rosmeulen, P. Jansen, K. Baert, L. Deferm: CMOS Compatible Wafer

Scale Adhesive Bonding for Circuit Transfer, Transducers 97, Intl. Conf. on Solid-State

Sensors and Actuators, Chicago, IL, pp. 629–632 (1997)

66. A.B. Frazier: Low Temperature IC-Compatible Wafer-to-Wafer Bonding with Embedded

Micro Channels for Integrated Sensing Systems, Proceedings of the 38th Symposium on

Circuits and Systems, Rio de Janeiro, Brazil, pp. 505–508 (1996)

67. R. Ghodssi, L.G. Frechette, S.F. Nagle, X. Zhang, A.A. Ayon, S.D. Senturia, M.A. Schmidt:

Thick Buried Oxide in Silicon (TBOS): An Integrated Fabrication Technology for Multi-

Stack Wafer-Bonded MEMS Process. Transducers ’99, 10th International Conference on

Solid-State Sensors and Actuators, Sendai, Japan, pp. 1456–1459 (1999)

68. Y.T. Cheng, L. Lin, K. Najaﬁ: Localized silicon fusion and eutectic bonding for MEMS

fabrication and packaging, J. Microelectromech. Syst. 9, 3–8 (2000)

69. Y.-T. Cheng, L. Lin, K. Najaﬁ: A hermetic glass-silicon package formed using localized

aluminum/silicon-glass bonding, J. Microelectromech. Syst. 10, 392–399 (2001)

70. Y.T. Cheng, L. Lin, N. Najaﬁ: Localized Silicon Fusion and Eutectic Bonding for MEMS

Fabrication and Packaging, Solid-State Sensor and Actuator Workshop, Hilton Head Island,

SC, pp. 233–236 (1998)

71. L. Lin: MEMS post-packaging by localized heating and bonding, IEEE Trans. Adv.

Packaging 23, 608–616 (2000)

72. L. Lin, Y.-T. Cheng, K. Najaﬁ: Formation of silicon-gold eutectic bond using localized

heating method, Jpn. J. Appl. Phys. 37, L1412–L1414 (1998)

73. L. Lin: Thermal challenges in MEMS applications: phase change phenomena and thermal

bonding process, Microelectron. J. 34, 179–185 (2003)

74. H.-A. Yang, M. Wu, W. Fang: Localized induction heating solder bonding for wafer level

MEMS packaging, J. Micromech. Microeng. 15, 394–399 (2005)

75. N. Ito, K. Yamada, H. Okada, M. Nishimura, T. Kuriyama: A Rapid and Selective Anodic

Bond Method, Transducers 95, 8th International Conference on Solid-State Sensors and

Actuators and Eurosensors IX, Stockholm, Sweden, pp. 277–280 (1995)

76. E.M. Chow, H.T. Soh, A. Partridge, J.A. Harley, T.W. Kenny, C.F. Quate, S. Abdollahi-

Alibeik, J.P. McVittie, A. McCarthy: Fabrication of High-Density Cantilever Arrays and

Through Wafer Interconnects, Solid-State Sensor and Actuator Workshop, Hilton Head

Island, SC, pp. 220–224 (1998)

77. A. Doll, F. Goldschmidtboeing, P. Woian: Low temperature Plasma-Assisted Wafer Bonding

and Bond-Interface Stress Characterization, IEEE MEMS, Maastricht, pp. 665–668 (2004)

78. G. Kräuter, A. Schumacher, U. Gösele: Low temperature silicon direct bonding for appli-

cation in micromechanics: bonding energies for different combinations of oxides, Sens.

Actuators A 70, 271–275 (1998)

79. U. Gösele, Y. Bluhm, G. Kästner, P. Kopperschmidt, G. Kräuter, R. Scholz, A. Schumacher,

St. Senz, Q.-Y. Tong, L.-J. Huang, Y.-L. Chao, T.H. Lee: Fundamental issues in wafer

bonding, J. Vac. Sci. Technol. A 17, 1145–1152 (1999)

80. J.E. Semmens, B.P. Scackmuth: Evaluation of Silicon on Insulator (SOI) Bonded Wafers

Using Automated Acoustic Micro Imaging, SMTA Pan Paciﬁc Symposium, Feb 10–12,

pp. 1–4 (Oahu, HI, 2004)

81. M. Reiche, S. Hopfe, U. Gösele, H. Strutzberg, Q.-T. Tong: Characterization of interfaces

of directly bonded silicon wafers: A comparative study of secondary ion mass spectroscopy

11 Wafer Bonding 877

multiple internal reﬂection spectroscopy, and transmission electron microscopy, Jpn. J. Appl.

Phys. 35, 2102–2107 (1996)

82. R.H. Esser et al.: Directional diffusion and void formation at a Si (001) bonded wafer

interface, J. Appl. Phys. 92(4), 1945–1949 (2002)

83. X.X. Zhang, J.-R. Raskin: Low-temperature wafer bonding: A study of void formation and

inﬂuence on bonding strength, J. Microelectromech. Syst. 14, 368–382 (2005)

84. T. Suni, J. Kiihamäki, K. Hettinen, I. Suni, J. Mäkinen,: Characterization of Bonded Interface

by HF Etching Method, Science, Tech, and Appl. VII ECS, Electrochemical Society

Meeting, pp. 70–75 (Orlando, FL, 2003)

85. M. Nese, A. Hanneborg: Anodic bonding of silicon to silicon wafers coated with aluminum,

silicon oxide, polysilicon or silicon nitride, Sens. Actuators A 37–38, 61–67 (1993)

86. E. Obermeier: Anodic Wafer Bonding, Proceedings of the 3rd International Symposium on

Semiconductor Wafer Bonding, ECS, Electrochemical Society Meeting, pp. 212–220 (Reno

NV, 1995)

87. R. DeReus, M. Lindahl: Si-to-Si Wafer Bonding Using Evaporated Glass, Proceedings of

Transducers ’97, Chicago, IL, USA, pp. 661–664 (1997)

88. D.V. Kubair, S.M. Spearing: Cohesive zone modeling of wafer bonding and fracture: Effect

of patterning and toughness variations, J. Phys. D: Appl. Phys. 39, 1050–1057 (2006)

89. S. Tatic-Lucic, J. Ames, B. Boardman, D. McIntyre, P. Jaramillo, L. Starr, M. Lim: Bond-

quality characterization of silicon-glass anodic bonding, Sens. Actuators A 60, 223–227

(1997)

90. T. Stratton, D. Burns, B. Speldrich: IEEE Workshop on Sensors and Actuators, p. 82 (Hilton

Head Island, SC, 1992)

91. M. Madou: Fundamentals of Microfabrication (CRC Press, Boca Raton, FL, 1997)

92. W.P. Maszara: Silicon-on-insulator by wafer bonding: A Review, Journal of Electrochem.

Society. 138, 341–347 (1991)

93. D. Hurd, R. Caretta, W. Gerberich: An experimental fracture mechanics study of a strong

interface: The silicon/glass anodic bond, J. Mater. Res. 10, 387–400 (1995)

94. S. Go, Y. Cho: Experimental evaluation of anodic bonding process based on the Taguchi

analysis of interfacial fracture toughness, Sens. Actuators A 78, 52–57 (1999)

95. K.N. Chen, C.S. Tan, A. Fan, R. Reif: Morphology and bond strength of copper wafer

bonding, Electrochem. Solid-State Lett. 7, G14–G16 (2004)

96. E. Reedy Jr, T. Guess: Comparison of butt tensile strength data with interface corner stress

intensity factor prediction, Int. J. Solids Struct. 30, 2929–293 (1993)

97. E. Reedy Jr, T. Guess: Butt joint strength: Effect of residual stress and stress relaxation,

J. Adhesion Sci. Technol. 9, 33–45 (1996)

98. E. Reedy Jr, T. Guess: Interface corner failure analysis of joint strength: Effect of adherend

stiffness, Int. J. Fracture 4, 305–314 (1998)

99. M. Dunn, W. Suwito, S. Cunningham: Fracture initiation at sharp notches under mode I,

mode II, and mild mixed mode loading, Int. J. Fracture 84, 367–381 (1997)

100. W. Suwito, M.L. Dunn, S.J. Cunningham, D.T. Read: Elastic moduli, strength, and fracture

initiation at sharp notches in etched single crystal silicon microstructures, J. Appl. Phys. 85,

3519–3535 (1999)

101. M. Dunn, S. Cunningham, P. Labossiere: Initiation toughness of silicon/glass anodic bonds,

Acta Mater. 48, 735–744 (1999)

102. P. Labossiere, M. Dunn: Stress intensities at interface corners in anisotropic bimaterials,

Eng. Fract. Mech. 62, 555–576 (1999)

103. P.E.W. Labossiere, M.L. Dunn, S.J. Cunningham: Characterization of wafer bond tough-

ness. In Semiconductor wafer bonding: Science, Technology, and Applications, Proceedings

Electrochemical Society, 196th Meeting, Oct 17–22, pp. 338–349 (Honolulu, HI, 1999)

This is Blank Page Integra xxxii

Chapter 12

MEMS Packaging Materials

Ann Garrison Darrin and Robert Osiander

Abstract This chapter discusses the differences between the heritage microcircuit

packaging world and the still evolving MEMS packaging arena. Materials used in

the packaging of MEMs are reviewed and their respective applications. The packag-

ing schemes for these devices owe their infrastructure base to the body of knowledge

surrounding semiconductors and microcircuits. MEMS devices yield new complex-

ities which drive new packaging solutions. As opposed to traditional microcircuit

chips, MEMS often include moving structures along with the need to have contact

with the external environment, driving the requirements for packaging such compo-

nents. Thus, some functions include interaction with the surrounding environment,

such as pressure sensors. This imposes new r equisites on packaging, since in reg-

ular microelectronics the chip must be protected completely from any impact from

the environment. Packaging also provides mechanical support to the sensitive chip,

facilitating the handling of the chip, and simplifying assembly. This chapter empha-

sizes the materials involved in packaging MEMS devices and the addresses the

challenges involved. Included in this chapter are several case studies demonstrating

novel packaging/material solutions.

12.1 MEMS Packages and Applications

Packaging for MEMs provides for power and signal paths; thermal manage-

ment; mechanical support; and environmental protection and/or interface protection.

MEMS pose numerous packaging challenges that often drive custom s olutions by

the very nature of their conﬁgurations and applications. Commercialized MEMS

products such as inkjets and airbag sensors use simple packaging solutions; but

devices that involve environmental interface have special requirements that drive

A.G. Darrin (B)

The Johns Hopkins University Applied Physics Laboratory, Laurel, MD, USA

e-mail: ann.darrin@jhuapl.edu

879

R. Ghodssi, P. Lin (eds.), MEMS Materials and Processes Handbook,

MEMS Reference Shelf, DOI 10.1007/978-0-387-47318-5_12,



Springer Science+Business Media, LLC 2011

880 A.G. Darrin and R. Osiander

novel approaches (i.e., bio-MEMS packages that need to handle ﬂuids). MEMS

packaging can be roughly divided into two areas: protection at the package level and

protection at the wafer or device level. At the package level, MEMS are often man-

ufactured following traditional military speciﬁcations that require robust hermetic

sealing technologies. This branch of the packaging industry transferred almost intact

from the semiconductor/microelectronics industry. However, this approach is in

rapid decline with the main trend being away from military speciﬁcations and their

high reliability electronics toward less expensive commercial, off-the-shelf (COTS)

electronics. The wafer-level packaging and protection of MEMS structures enable

low cost, high volume production packages that are not hermetically sealed; e.g.,

plastic packages or tailored RF packages with optimized electrical performance.

The fact that MEMS often must be in contact with the operating environment is the

most important distinction between packaging of MEMS and microelectronics.

MEMS packaging protects the mechanical structures during wafer dicing, assem-

bly, and operation [1]. For example, during the singulation step, a mask or a

wafer-level technique is used to protect vulnerable motion components as the most

common MEMS packaging requirement is protection without restricting mechan-

ical action in a cavity device. Microcircuit packaging techniques are often over

molded with encapsulant contacting the chips and restricting motion and cannot

be used as a MEMS packaging technique without redesign.

The hermetic cavity package used extensively in the microcircuit world, espe-

cially in critical end item applications, has been adopted for the packaging of

MEMS. These standard hermetic packages are a costly solution but do offer full

hermetic isolation. With respect to cost, a prevailing opinion has been that MEMS

packaging is expensive. This has caused developers to question the application and

the requirements, especially when hermetic packaging is speciﬁed. For example, is

hermetic packaging truly required or just a dry, hydrophobic package or perhaps

only a constant atmosphere is needed [1]? Early MEMS accelerometer packages

were hermetic cavity designs that allowed space for motion, although these ceramic

packages have since been replaced with more cost effective designs. I nertial sensor

applications require only electrical inputs and outputs and do not have the packag-

ing challenges such as in bio-MEMS where ﬂuid transport is incorporated. MEMS

packaging options range from full hermetic, near-hermetic, and non-hermetic sin-

gle packages to wafer-level packaging techniques. The materials for each of these

packaging classes are discussed.

12.1.1 Packaging Classes

Protection at the package level is provided by full hermetic, near-hermetic, and non

hermetic packaging solutions. Full hermetic packages evolved from glass to metal

and ceramic in the semiconductor/microcircuit world and are used in MEMS pack-

aging schemes. The near-hermetic package is used where full hermetic seal is either

not required or is driven by a speciﬁc product application. The non-hermetic plastic

package is widely used in the microcircuit community for high volume low cost

12 MEMS Packaging Materials 881

packaging. In a plastic package, the chip is typically attached to a metal leadframe

by wire bonding followed by epoxy overmolding. The overmolding compound is a

mix of solid epoxy resins, hardeners, ﬁllers and additives that is heated to polymer-

ize the material. This mold compound makes direct contact with the die, wire bonds

and leadframe. This technique cannot be translated directly to MEMS without an

intermediate protection solution such as capping the chip. Capped chips may then

be packaged using this technique.

Protecting chips at the wafer-level is normally done through capping and a multi

step partial packaging process. Caps are passive with no electrical paths and must

allow access to chip bond pads. In this partial wafer level packaging the most com-

mon solution is to singulate caps ﬁrst using a multi-step process and later s ingulate

the MEMS wafer. To eliminate the extra steps of the multi step partial wafer level

package, full wafer level packaging (WLP) involves incorporating the interconnect

structure through the chip or cap. This allows the cap layer to be singulated dur-

ing the MEMS sawing step. For applications requiring gas and ﬂuid transport, the

capping wafer level solutions have yet to be developed.

12.1.2 MEMS Versus Microcircuit or Integrated Circuit Packaging

The highly integrated circuits of today have evolved after generations of iterations

that started with the germanium transistor. The packaging schemes for MEMS

devices owe heritage to the body of knowledge surrounding semiconductors and

microcircuits. However, the MEMS device yields new complexities that drive

new packaging solutions. Table 12.1 demonstrates these differences between the

microcircuit and the MEMS world.

As opposed to traditional microcircuit chips, MEMS packaging must consider

moving structures and contact with the external environment. Some applications

include direct interaction with the surrounding environment, such as pressure

sensors. This imposes new requirements on packaging, since in traditional micro-

electronics the chip must be protected completely from any impact from the

environment. MEMS packaging can also provide mechanical support to the sensitive

chip, facilitate handling of the chip, and simplify assembly.

12.1.3 Application Drivers and Interfaces

The process of selecting materials, packages, processes and techniques for MEMS

is driven by the end item application. For example, in an RF end item application,

a major design problem is to have controlled impedance of the input and output

signals. Therefore, the package should not limit the electrical performance of the

MEMS components.

Another application driven requirement is the need for hermeticity. Designers

must decide if their components need to be isolated from oxygen, nitrogen, ambient

882 A.G. Darrin and R. Osiander

Table 12.1 Microcircuits packaging versus the complexity of MEMS packaging

Microcircuit

packaging solutions MEMS

MEMS packaging

solution

Structures with no

moving parts and

may be stacked

Easy to assemble and

mass produce

3-D structures which

may involve delicate

components and

precision movements

Require application

speciﬁc packaging

often with cavities

or vacuum spaces

Packaging styles are

often generic or

independent of

application

Industrial and military

standards exist

Applications are a

variety of speciﬁc

functions such as

biological,

chemical,

electromechanical

and optical

Packaging styles are

application driven

and custom t o

unique functions

Packaging techniques

are mature

Paths to follow for

design, material

selections,

fabrication

processes and

reliability and

assurance testing

Mature packaging

techniques may not

work for most

applications

New packaging

schemes must be

developed at the

design concept

phase

IC are protected from

the environment

Environmental

protection is

straightforward and

provided by sealed

encapsulation

In many applications

sensitive moving or

stationary

components are

interfaced with

with the environment

Complex balance of

protection from and

access to the

environment is

required

IC transmits power for

speciﬁc electrical

operations

Only external ties are

through inductive or

conduction coupling

Many components and

functions are required

within the package

Increased complexity

and interfaces

provide new failure

mechanisms

moisture, etc. before making a decision on what level of hermetic packaging is nec-

essary. For example, ambient moisture often deteriorates MEMS devices, however,

in the instance the package needs only to be a dry package and not fully hermetic.

Then, the use of appropriate getters will sufﬁce; but if long-term reliability is a

requirement, the packages still need to be near hermetic since the getters have a

limited capacity [1]. Figure 12.1 shows a variety of ceramic package structures for

sensor applications.

12.1.4 Interfaces to Other System Components

As the package is the primary interface between the MEMS and the system, it must

be capable of transferring operating power and a multitude of signals. In addition,

the package may be required to distribute both operating power and other signals to

other components inside the package. The integration of more MEMS devices and

12 MEMS Packaging Materials 883

Fig. 12.1 A variety of ceramic package structures for sensor applications (Reprinted with

permission of the Kyocera Corporation)

other components into a single package increases the packaging complexity as the

number of interconnects within the package increases.

12.1.4.1 Power and Signals Interface

When designs require high frequency RF signals, they can be introduced into the

package along metal lines passing through the package walls, or they may be elec-

tromagnetically coupled into the package through apertures in the package walls.

RF energy losses between the MEMS device and the system can be due to radiation,

by reﬂection from components that are not impedance matched, or from disconti-

nuities in the transmission lines. The ﬁnal connection between the MEMS and the

DC and RF lines is usually made with wire or ribbon bonds; although ﬂip-chip die

attachment and multi-layer interconnects, using thin dielectrics have also been used.

12.1.4.2 Optical Interface

In the rapid telecom growth period of the late 1990’s and into the 2000’s, optical

MEMS devices gained considerable attention in the telecommunications industry,

particularly in the optical networking and switching arenas. Since optical MEMS

are micro-systems, which rely on high precision optics, electronics, and mechan-

ics working in close concert, these emerging devices pose some unique packaging

challenges yet to be addressed by the general packaging industry.