24 Micro- and Nanomanufacturing
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(a) Schematic cross sectional view
of the field effect transistor FET
to show the growth profile of the
GaAs/AIGaAs material.
Gale tentfth
(b) Schematic diagram of
GaAs/AIGaAs heterostructure FET.
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EtchUnch
Sobslratc
Junmin Hu, et
al.,
"Using soft lithography to fabricate GaAs/AIGaAs heterostructure field effect
transistors," Appl. Phys. Lett., Vol.
71,
No. 14,
6
October 1997.
Fig. 1.23. Schematic diagram
of
a GaAs/AIGaAs field effect transistor produced
using soft lithography [11]
/ "^j^y
GaAs/AlGau\s
AlNiGr contacts
Quai
Iz
slide
(b)
^
/
Schematic illustration of the procedure
for ESS fabrication^
(a) Fir.st MIMIC using polyiirethane
(PU) to define the ohmic contacts
and alignment marks.
Cure PU, peel off the first PDM.S
mold, and remove the PU under-
layer using oxygen R.1E,
Evaporate AlNiGe, lift ofl PU, and
anneal to form the ohmic contacts
for
the source and drain.
Regi.ster, second MIMIC to define
etch trenches.
Cure PU, peel off the second PDMS
mold, and remove the underlayer
using oxygen PIE.
Etch in citric acid and hydrogen
perox-ide .solution
to
remove the two
degree angle in the etch trenches.
Register, third MIMIC to define the
gate.
Cure PU, peel off the third PDMS
mold, and remove the underlayer
using oxygen RIE.
Evaporate Cr/Au and lift
olT
PU
to
form the gate.
Cleave two ends to reitiove the two
degxee angle in these region.s.
Fig.
1.24.
Schematic illustration
of
the manufacturing procedure
for
producing
a
field effect transistor using soft lithography [11]