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24 T.L. Lamers and B.L. Pruitt

Fig. 1.14 Micromechanical ﬂexures require a large ratio of fracture strength to Young’s mod-

ulus (First appearing in Srikar and Spearing [53]. Modiﬁed ﬁgure. Reprinted with permission.

materials (not contributing to the structure) as sacriﬁcial materials in the fabrication

ﬂow. Attributes of concern t o the design process include the material properties,

net shape of the device including surface roughness and tolerances, the process-

ing constraints on pressure, temperature, and materials interfaces/compatibilities.

For example, many MEMS devices are integrated with CMOS electronics and thus

are limited in their processing materials set, equipment, and temperature. Most

CMOS integrated circuits (ICs) should be kept below 300

◦

C once the I C devices

are fabricated. Selecting the best process for a given geometry and material requires

screening of available process capabilities, ranking of available processes, and

detailed comparisons of their merits in terms of dimensional control, roughness,

stress, temperature, and so on. D. J. Quinn et al. proposed a systematic classiﬁca-

tion of process chains for standard processes and materials capabilities (Table 1.1).

For ﬁrst-iteration concept generation, the proposed process attributes charts show

achievable dimensional space for beams versus trenches as a function of process for

process capabilities published as of 2006.

Quinn et al. further develop process attributes charts for tolerances achievable

by the process capabilities of 2006 (Fig. 1.15). For ﬁrst-order design selection of

process with material, they present a case for the design space of a piezoresistive

pressure sensor and treat the membrane with constraints similar to beam process

capabilities in Fig. 1.15. Such process selection charts are especially helpful in

guiding a designer selecting from a range of process capabilities reported in the

literature versus in-house capabilities. However, the materials and process selection

charts inherently assume the embodiment of the design concept is already known.

A company entering a new market or a student entering a new research area will

beneﬁt from a full design cycle to generate and select the best concepts meeting

customer requirements. Concept selection, discussed in Section 1.2, can guide the

1 The MEMS Design Process 25

Table 1.1 Process chains and capabilities

Process Chain Family Process Chain Name Fabrication Sequence Summary

Primary

Material

Secondary

Material(s)

Bulk

Micromachining

Wet Etch Anisotropic Wet Etching of (100)

Si–KOH

Deposit mask material; pattern; etch;

remove mask material (if desired)

Si SiO

,SiN

Anisotropic Wet Etching of (110)

Si–KOH

Deposit mask material; pattern; etch;

remove mask material (if desired)

Si SiO

,SiN

Anisotropic Wet Etching of (100)

Si–TMAH

Deposit mask material; pattern; etch;

remove mask material (if desired)

Si SiO

,SiN

Anisotropic Etched Beam in (100)

Si–KOH

Deposit mask material; pattern;

underetch / release beam

SiN Si

Anisotropic Wet Etching of (100)

Si–EDP with P++ Etch Stop

Thin wafer; boron diffuse and drive in;

deﬁne mask and pattern; etch

Si SiO

,SiN

Dry Etch Anisotropic Dry Etching (RIE) of

Si – Metal Mask

Deposit (electroplate) metal mask and

pattern; RIE; remove mask

Si Metal (Ni)

Deep Etch, Shallow Diffusion Process Deposit mask material; RIE; boron

diffuse; short RIE; release OR bond

to glass, thin and release

Si Metal (Ni)

Dissolved Wafer Process Etch anchor recesses; boron diffuse

and drive in; pattern structure; etch

recess in glass; bond Si wafer to

glass; thin wafer; EDP etch

Si Glass

SCREAM – Si (Thick Oxide Mask) Short thermal oxidation and pattern;

RIE; long (thick) thermal oxidation;

RIE; thermal oxidation of sidewalls;

deposit metal; deposit resist;

isotropic release etch

Si SiO

SCREAM I – Si (Deposited Oxide

Mask)

Deposit mask oxide and pattern; long

RIE; deposit sidewall oxide; short

RIE; long RIE; isotropic release

etch; deposit metal

Si SiO

26 T.L. Lamers and B.L. Pruitt

Table 1.1 (continued)

Process Chain Family Process Chain Name Fabrication Sequence Summary

Primary

Material

Secondary

Material(s)

SCREAM II – GaAs Deposit nitride mask and pattern; RIE;

deposit nitride layer; deposit metal;

spin on resist, bake and remove;

RIE exposed metal; RIE nitride;

isotropic release etch

GaAs SiN

Deep Reactive Ion Etching (DRIE –

Bosch Process)

Deposit mask and pattern; short

isotropic etch (SF6); passivate

sidewalls (C4F8); repeat to desired

depth

Si C

Trilayer Mask Dry Etch Process with

Thermal Oxidation Finishing

Deposit mask layer #1 (metal); deposit

mask layer #2 (resist and bake);

deposit mask layer #3 (metal);

pattern trilayer mask (RIE); RIE;

thermal oxidize sidewalls; isotropic

wet (ﬁnishing) etch of sidewalls

Si Ni, SiO

Surface Micromachining Polysilicon Surface Micromachining Deposit isolation layer (if desired);

deposit sacriﬁcial layer

(densiﬁcation bake if necessary);

open up anchors in sacriﬁcial layer;

deposit structural (polysilicon layer)

and anneal (if necessary); pattern

structure (RIE); wet isotropic

release etch of sacriﬁcial layer

PolySi PSG,

SiO

1 The MEMS Design Process 27

Table 1.1 (continued)

Process Chain Family Process Chain Name Fabrication Sequence Summary

Primary

Material

Secondary

Material(s)

Silicon Carbide Surface

Micromachining

Deposit isolation layer (if desired);

deposit sacriﬁcial layer; open up

anchors in sacriﬁcial layer; deposit

structural (Silicon Carbide); pattern

structure (RIE); wet isotropic

release etch of sacriﬁcial layer

SiC Si, PSG,

SiO

Polyimide Surface Micromachining Deposit isolation layer; deposit

sacriﬁcial layer; spin-on thin

polyimide layer and partial cure;

deposit conductor layer (if

necessary); alternate spin casting

and soft baking for remaining

structural depth; ﬁnal cure; deposit

metal mask and pattern; plasma

etch; isotropic release etch

Polyimide PSG,

SiO

Multilayer Polysilicon Surface

Micromachining (Sandia SUMMIT /

SUMMIT V)

Deposit buffer/isolation layer; deposit

sacriﬁcial layer; deposit structural

(polysilicon) layer; planarize using

CMP; repeat to desired height up to

5 structural layers; wet isotropic

release structure

PolySi PSG,

SiO

Soft Lithography Processes E-beam Deﬁned, Hard Master Mold

Making (Nano-scale Molds)

Thermal oxidize layer and pattern

(e-beam); RIE

Si, SiO

SiO

Micro-contact Printing (μCP) Ink master stamp with pattern

material; transfer patter to target

material (press); use pattern as etch

or deposition mask (if desired)

“Inks”

(polymers,

SAMs etc.)

PDMS

(Master

Material)

28 T.L. Lamers and B.L. Pruitt

Table 1.1 (continued)

Process Chain Family Process Chain Name Fabrication Sequence Summary

Primary

Material

Secondary

Material(s)

Micro-molding in Capillaries (MMIC) Press PDMS master mold against

target substrate; insert liquid

polymer via capillary action and

cure; remove mold

Polymers PDMS,

SiO

Micro-molding in Capillaries

(MMIC) – Vacuum Assisted

Press PDMS master mold against

target substrate; insert liquid

polymer via vacuum action and

cure; remove mold

Polymers PDMS,

SiO

Micro Replica Molding (REM) Cast and cure PDMS against hard

master mold (Si, SiO

,orSU8)and

remove

PDMS PDMS,

SU8, Si

(Master

Material)

Micro Transfer Molding (μTM) Fill master PDMS mold with liquid

polymer; press / pattern against

substrate; remove excess polymer

and cure; remove mold

Polymers PDMS

Hard Master Embossing /

Nano-Imprint Lithography (NIL)

Deposit polymer; imprint pattern into

deposited polymer and cure;

complete pattern transfer with RIE;

deposit metal on patterned polymer

and lift off

Polymers SiO

LIGA Deposit thick resist layer (PMMA);

X-Ray pattern and develop;

electroplate metal and release

Metal (Ni) PMMA

Modiﬁed ﬁgure used with permission of IEEE. First appearing in Quinn et al. [54]

1 The MEMS Design Process 29

Fig. 1.15 Dimensional capabilities for beams ( top) and trenches (bottom) versus process selection

(Modiﬁed ﬁgure used with permission of IEEE. First appearing in Quinn et al. [54])

30 T.L. Lamers and B.L. Pruitt

process of selecting a design concept, including embodiment and fabrication pro-

cess. The design process should further determine if a MEMS concept is the best

solution or at least is competitive with existing macroscale solutions on performance

metrics.

1.6 Evaluate Concepts

1.6.1 Modeling

Much as in materials selection, the level of detail in modeling device performance

increases as the design advances from a concept to embodiment as a prototype

and product. Analytical models using closed-form electrical or mechanical relation-

ships are available in most MEMS textbooks [36, 55, 56]. These models should

be employed during and after brainstorming of concepts expected to meet customer

requirements (this stage is based somewhat on team experience) and certainly before

concept screening of the top candidates. Once a design is advanced toward prototyp-

ing plans, short loops for a more detailed analysis of materials properties and process

capabilities should be undertaken. This phase may require short fabrication loops

to deposit and characterize ﬁlms or test structures. Finite element software such

as COMSOL

or ANSYS

enables multiphysics coupled modeling between

domains such as mechanics, electromagnetism, ﬂuidics, and thermal. This level of

prediction will enable design for baseline performance as well as local optimization

iterations and sensitivity analysis via scripting. Some analysis and design software

providers (e.g., Coventorware

) seek to provide a suite of tools to designers from

layout to process tolerance analysis. The designer must still gather the requisite

information about her process before building the model and must have materials,

geometry, and a process ﬂow in hand. A large company can build a database of their

tool capabilities and process speciﬁcations for ﬁxed process recipes.

For example, for Avago’s microphone design process, the mic was modeled

ﬁrst by coupling thin-plate bending theory equations, taken from Timoshenko

and Woinowsky-Krieger [57], with piezoelectric electromagnetic and stress–strain

constitutive relations to produce an estimated potential difference across the piezo-

electric membrane as a function of a uniformly applied pressure. Finite element

analysis (FEA) using ANSYS with the multiphysics solver conﬁrmed the theoreti-

cal results. Theoretical analysis provided the ability to make quick tradeoffs between

a few general parameters, such as membrane size or piezoelectric ﬁlm thickness,

but FEA provided a more effective means for making detailed design decisions.

Rapid-turn prototype manufacturing was also done simultaneously with theoreti-

cal analysis and FEA. As results of theoretical analysis and FEA became available,

they were incorporated into layouts. Layout of more than one set of designs was

often done simultaneously as simulation, intuition, and data offered insight into

new possibilities, without waiting for full test characterization of the previous set

of designs. As test data became available, they also guided design decisions. Details

of the Avago modeling efforts can be found in [43, 50].

1 The MEMS Design Process 31

1.7 Optimization and Other Design Methods

1.7.1 Design Optimization

Once a baseline transduction mechanism, device geometry, materials, and process

are known, optimization techniques are useful to determine critical parameters and

combinations of parameters contributing to local optimum performance via numer-

ical, analytical, and statistical-based simulation, design of experiments, sensitivity

analysis, or Pareto optimal techniques. Such techniques can be applied to account

for geometric design with tolerances related to process uncertainty and material

properties uncertainty [58]. Sensitivity analyses (variability of the desired output

parameter with small changes in input control parameters) in different domains

have been presented with optimization performed by trading off subsets of criti-

cal parameters while other process parameters remain ﬁxed [35, 59–64]. Design

of experiments (DOE) is an alternative approach where the settings of various

parameters are changed over experimental runs such that the effect of varying each

parameter as well as interactions between parameters can be calculated [65]. The

DOE approach requires more time spent in upfront experimental planning versus

approaches that vary one parameter at a time, but the knowledge of parameter

interactions gained can be crucial.

1.7.2 Uncertainty Analysis

The designer must consider the sources of uncertainty in the output parameter of the

device or system [66]. Uncertainty analysis (e.g., root mean sum of square errors)

can reveal the input dimensions and properties that require the most attention to

mitigate their tolerance effects on performance, to measure their as-fabricated values

during the process, or that require ﬁnal calibration but govern linearity, repeatability,

and hysteresis of the output. Manufacturability and reliability can be assessed if the

critical dimensions and parameters of the design are identiﬁed and compared to

available process capabilities. Parameterized wafer layouts and process maps can

help determine how t o adjust or compensate designs versus wafer position in a lot

[67, 68].

Most optimization studies assume a priori material and process selection and

look for Pareto-optimal designs, meaning designs that provide optimal results

given known uncertainty distributions of material and fabrication properties and

tolerances. Probabilistic methods, such as Monte Carlo simulation, have also been

applied to MEMS to predict reliable operation given variability in dimensions and

operating parameters [69]. Of course before this level of optimization, the designer

must make materials and process selections, and potentially fabricate and test initial

devices.

1.7.3 FMEA

Failure modes and effects analysis (FMEA) is a design method typically used during

the development process to assess weak aspects of the design or process [70]. Those

32 T.L. Lamers and B.L. Pruitt

aspects are then targeted for improvement. FMEA can also be used on products

currently in production to evaluate problem areas ripe for redesign.

Of the few reports in the literature documenting design methods applied to

MEMS, FMEA and optimization methods (on a settled design architecture) are the

most commonly applied. In several cases FMEA has delivered substantial results on

MEMS programs:

Agilent Technologies used FMEA on their FBAR products to improve yield in

new products. Over several generations of technology development utilizing FMEA,

typical wafer level yields rose from less than 50% to well above 50%, signiﬁcantly

reducing product cost [43].

Texas Instruments’ use of FMEA on their digital micromirror device (DMD)

is one prominent example of the application of FMEA to MEMS. Starting in

approximately 1992, TI began performing FMEA on every new DMD design and

each major design change. These efforts are described in several papers by M. R.

Douglass [40, 41]. Using FMEA helps TI maintain good reliability and perfor-

mance in addition to rapid development cycles, resulting in faster time to market

with larger margins and lower risk of failures [40, 41]. Development is stream-

lined by identifying testing and process development needs prior to testing units.

FMEA enables the development team to avoid problems later in development or

in production by predicting high-risk areas to focus on early in product devel-

opment. Once high-risk items have been identiﬁed, the team develops methods

to test for those issues, testing to failure to explore the limits of the DMD. This

method uses stress levels far in excess of product speciﬁcations to identify design

weaknesses [41].

As units failed, the results were investigated to determine whether pro-

cess or design changes were warranted. In some cases where changes could

be made easily, modiﬁcations were implemented regardless of whether they

were needed to meet product reliability speciﬁcations. According to Douglass,

“These decisions resulted in further improvements to DMD robustness, resulted

in large margins, and provided ﬂexibility for tradeoffs during future development

activities” [41].

For each proposed change, the product engineer coordinates gathering the appro-

priate inputs for the FMEA. Characterization tests are then performed. TI credits

FMEA for much of the robustness, reliability, and commercial success of the DLP

projection systems [41, 70, 71].

1.7.4 Design Method Timing

The MEMS designer is referred to Fig. 1.3 again to observe that the successful

process is not linear but rather involves multiple iterative loops to uncover the pro-

cess and material parameters particular to his facilities, the dimensional tolerances

applicable to the combination of geometry, dimensions, and processes proposed,

and evolving models of their relationship to overall device and system performance.

Critical parameters may not be observable in the ﬁnal device output, for example,

1 The MEMS Design Process 33

resonator performance is coupled to several geometric parameters, material prop-

erties, and packaging induced stresses and isolation ability. The designer should

consider how to independently observe and account for these process variables. The

overall performance of the device should include typical sensitivity and resolution

speciﬁcations, but also metrics including reliability, cost, yield, and repeatability,

which are difﬁcult to predict at the outset of the design process but become more

apparent through careful evaluation of test structures and process steps. The rela-

tive complexity and cost of design concepts, as well as how well concepts ﬁt user

requirements can be evaluated through structured design methodologies that will aid

the designer in selecting the best concepts to carry forward through prototyping and

production.

1.8 Summary

This chapter provided examples of design methods that can be applied to MEMS

development programs to s treamline and shorten the development process. The

product development process is shown via ﬂowchart in Fig. 1.3, highlighting

the product deﬁnition steps and stakeholders. Options for both market-pull and

technology-push projects are demonstrated in the ﬁgure, as well as described in the

Knowles and Avago case studies, respectively. QFD Phase I and concept screening

are highlighted as tools that can be readily applied to MEMS projects. These tools

can help determine the most critical technical aspects of the product from a user

perspective, the most viable design concepts to prototype, and the best market ﬁt for

a technology, ultimately r esulting in faster time to market and increased likelihood

of market success.

Acknowledgments We dedicate this chapter to the late Professor Kos Ishii of Stanford University

who championed design methodologies across engineering disciplines; he was a friend, a men-

tor, and an inspiration to the authors. The authors are grateful to Dr. Markus Lutz, Dr. Robert

Candler, and Dr. Pete Loeppert for helpful discussions and suggestions. The authors thank the

Avago Technologies FBAR development team, particularly Shane Fazzio and Atul Goel, for their

assistance on the acoustic sensor work. Dr. Pruitt was supported in part by the National Science

Foundation (NSF) under CAREER Award ECS-0449400, COINS NSF-NSEC ECS-0425914, CPN

PHY-0425897, Sensors CTS-0428889 and NER ECCS-0708031. Dr. Lamers was supported in part

by an NSF Graduate Research Fellowship.

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