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Chapter 8

MEMS Wet-Etch Processes and Procedures

David W. Burns

Abstract Wet chemical etching through openings in photoresist or hard masks

underlies many process sequences for MEMS device fabrication. This chapter

presents more than 800 wet-etch recipes for over 400 varieties and combinations

of substrates and deposited thin ﬁlms, with emphasis on processes that use lab-

oratory chemicals often found in university and industrial cleanrooms. Over 600

citations serve as additional resources for selecting or developing etchants suitable

for processing MEMS devices. Nearly 40 tables, organized internally by material

then by etch components, allow quick location and comparisons among recipes.

Abbreviations for target materials and etch components are standardized to aid in

comparisons. Etch rates and etch selectivities over other materials are given where

available. While emphasizing silicon and other popular materials in the MEMS ﬁeld,

III-V compounds and more exotic materials are also presented.

Topics addressed include wet-etch principles and procedures; process architec-

tures that incorporate wet-etch sequences; evaluation and development of wet-etch

procedures and equipment with emphasis on safety and an anticipation of foundry

transfer; oxide, nitride, silicon, polysilicon, and germanium isotropic etching;

standard metal etching; nonstandard dielectric, semiconductor and metal etching;

photoresist removal and wafer cleaning sequences; silicide etching; plastic and poly-

mer etching; anisotropic silicon etching; bulk silicon and silicon–germanium etch

stops; electrochemical etching and etch stops; photoassisted etching and etch stops;

thin-ﬁlm etch stops; sacriﬁcial layer removal; porous silicon formation; layer delin-

eation for failure analysis; and defect determination. Practical examples offer some

of the ﬁner nuances in the processes and procedures related to wet chemical etching.

This chapter provides a practical and valuable guide for device designers and pro-

cess developers to select or develop an etch for many types of MEMS and integrated

MEMS devices.

D.W. Burns (B)

Burns Engineering, San Jose, CA, USA

e-mail: dwburns@pacbell.net

457

R. Ghodssi, P. Lin (eds.), MEMS Materials and Processes Handbook,

MEMS Reference Shelf, DOI 10.1007/978-0-387-47318-5_8,



David W. Burns 2011. Published by Springer Science+Business Media, LLC, with permission.

458 D.W. Burns

8.1 Introduction

Few micromachined or integrated devices are developed or manufactured without

some level of wet chemical processing. Whether the device is electrical, mechanical,

electronic, integrated, optical, optoelectronic, biological, polymeric, microﬂuidic,

sensor, or actuator, decisions about processing and process alternatives can have a

major impact on the ultimate technical and commercial success. These devices are

generally built on substrates of silicon, compound semiconductors, glass, quartz,

ceramic, or plastic involving one or more layers of thin ﬁlms deposited that are each

patterned and etched on the substrate. The layers and deposition sequence place

constraints on the process architectures and unit processes available for developing

and manufacturing the device, becoming increasingly complex and interactive as

the number of layers increases.

Wet etching is the systematic intentional removal of material using a liquid

etchant, a process step generally preceded by the formation of an overlying pho-

toresist mask (an exposed and developed photosensitive polymer) or a hard mask

(a patterned etch-resistant material). The etch step is generally followed by a rinse

step with deionized water and subsequent removal of the masking material. Wet-

etch alternatives include dry etching, which uses one or more gaseous reactants at

generally reduced pressures having RF-induced excitation of the reactant species

and vacuum pumping for removal of the reaction products. Nonplasma dry etch-

ing, such as xenon diﬂuoride or hydroﬂuoric acid vapor etching, has many of the

characteristics of a wet isotropic etch and is generally performed in a conﬁned

chamber.

The creation of nearly all types of IC, MEMS, MOEMS, MST, and NEMS

devices is likely to have involved some type of wet-etch procedure. Represented

as steps or sequences in the overall process ﬂow, wet etches are often incorporated

for selectively removing portions of deposited thin ﬁlms, stripping speciﬁc materi-

als such as hard masks and photoresist masks, cleaning and preparing substrates for

further processing, removing sacriﬁcial layers and portions of substrates, and form-

ing two- and three-dimensional structures. Considerations for a wet-etch sequence

include etchant availability, etch selectivity, etch rate, etch isotropy, material com-

patibility, process compatibility, process repeatability, cost, equipment accessibility,

worker safety, facilities support, and proper disposal concerns.

Although a device designer, process architect, or manufacturer may prefer a com-

pletely dry process ﬂow when available, many of the standard process steps such as

photoresist developing and wafer cleaning still remain aqueous. Wet-etch processing

sequences can offer cost, speed, and performance beneﬁts over dry-etch techniques.

Dry-etch analogues may be unavailable, such as for extensive selective undercut-

ting of microstructures or for crystal orientation-dependent etching. Dry processes

may be preferred over wet processes, particularly if available in a well-equipped

processing facility or if wet processes offer inadequate performance. An advantage

for utilizing wet processes, however, is that devices may be developed and manufac-

tured in a relatively low-capital, low-overhead laboratory or processing facility. Wet

etching becomes particularly attractive when dry etching requires long etch times in

8 MEMS Wet-Etch Processes and Procedures 459

an expensive plasma or RIE etching system, and can be more cost and time effective

when lots of 25 wafers or more are processed simultaneously.

The selection of processing sequences, whether wet or dry, is strongly driven

by the availability of equipment and processes to the developer at an associated

facility. The successful designer, developer, and manufacturer will nearly always

use or modify processes that are on hand and avoid additional requirements unless

absolutely necessary to develop new processes, install new equipment, or acquire

new process capability. It is important to understand and apply both wet and

dry processes where needed and to use standard processes wherever possible.

Table 8.1 summarizes general considerations for comparisons between wet and dry

etching.

Table 8.1 General comparisons between wet and dry etching

Consideration Dry etching Wet etching

1 Etch existence High High

2 Etch rate Moderate, variable High, variable

3 Etch uniformity Moderate, variable Moderate, variable

4 Material selectivity Low, variable High with careful selection

5 Wafer throughput Moderate High

6 Mask selectivity Moderate, variable High with careful selection

7 Photoresist mask usage High Not usable in some cases

8 Patterned feature resolution High Moderate

9 Substrate backside exposure Low High

10 Etch reliability High Moderate; improves with

automation

11 Etch repeatability High Moderate; improves with

automation

12 Training and maintenance Moderate Low

13 Operator chemical exposure Low Moderate

14 Unit process cost Moderate Low

15 Equipment cost High Low

16 Facilities cost High Low

This chapter begins with an overview of principles and process architectures for

wet etching, followed by a section on the evaluation and development of wet-etch

facilities and procedures for the local and remote user. The next two sections present

wet-etch processes in artiﬁcial yet practical divisions as IC-compatible materials

that are generally acceptable to integrated circuit manufacturers and nonstandard

materials that may require separate or dedicated equipment, facilities, postprocess-

ing, or other special considerations. Additional sections cover anisotropic etching

of silicon and etch stops, sacriﬁcial layer removal using wet etchants, porous silicon

formation, and wet etchants for layer delineation and defect determination. Further

discussions of wet etching techniques and processes can be found in many excellent

books and journals [1–30].

460 D.W. Burns

8.2 Principles and Process Architectures for Wet Etching

The t riumviral sequence of deposition, pattern, and etch dominates much of semi-

conductor and MEMS processing, as shown in typical process or fabrication

run travelers. The deposition sequence may include additive-process steps such

as epitaxial growth, e-beam evaporation, sputtering, chemical vapor deposition

(CVD), low-pressure CVD (LPCVD), metal-organic CVD (MOCVD), and plasma-

enhanced CVD (PECVD), and alternatively include other sequences such as thermal

oxidations or ion implantation. The patterning sequence generally involves spin-

depositing photoresist and exposing with a contact aligner, stepper, or e-beam

lithography system using a prescribed photoresist thickness and exposure time. The

thickness and exposure time may be adjusted as needed to ensure adequate fea-

ture deﬁnition, particularly over large changes in ﬁlm heights. The etching steps are

often plasma or reactive-ion based. In situations where dry etching is not available or

otherwise inadequate for a particular etch sequence, wet-etch steps can be inserted

into the process ﬂow. Selection of a particular wet- or dry-etch sequence is usually

determined during the design and development of a MEMS device, although the

choice may be modiﬁed when equipment is upgraded or the process is transferred

to another facility.

Various process architectures are available or can be created for MEMS devices,

such as fully integrated or fully custom processes, semicustom or s tandard MEMS

processes, process variants of other established processes, and unit processes from

multiple facilities, as illustrated in Fig. 8.1. Fully integrated MEMS processes can

be based on established CMOS, BiCMOS, or compound semiconductor processes.

Fully custom processes generally have only a few masking levels in a dedicated pro-

cess used for prototypes, initial production, or high-volume devices. Semicustom

processes incorporate device-speciﬁc MEMS sequences prior to or after integrated

circuit processes, and may be incorporated at either the wafer or die level. Standard

MEMS processes include qualiﬁed single and multilayer poly processes, metal pro-

cesses, SOI or LIGA processes, and multiuser or multidevice processes. Process

variants include relatively minor adjustments to an established process, such as

starting material variations, small changes to ﬁlm thickness or etch depths, and

elimination of feature-free patterning steps from a standard process ﬂow. For those

willing to transport wafers between multiple facilities, unit process steps may be

executed at one or more of the many excellent smaller facilities that have speciﬁc

capabilities and expertise such as thin-ﬁlm deposition, epi growth or ion implanta-

tion, patterning and etching, chemical–mechanical polishing, and backend processes

such as dicing and packaging.

Fully integrated and standard MEMS processes often provide the user with few

if any choices in the etchant determination, inasmuch as these processing sequences

are established and qualiﬁed at a particular facility. The user may not even know or

need to know details of the etch sequences. An exemplary fully integrated process

has IC sequences intermingled with qualiﬁed and compatible MEMS sequences.

Fully custom MEMS processes provide the widest opportunities for selection of

wet- and dry-etch sequences, particularly for early-stage device development, for

8 MEMS Wet-Etch Processes and Procedures 461

Process

Architectures

-CMOS

- BiCMOS

- Compound Semiconductor

Process

Variants

Semi-Custom

Fully

Custom

Standard

MEMS

Unit

Processes

Fully

Integrated

- Starting Material

- Film Thickness

- Etch Depth

- Omitted Mask Levels

- Pre-Processing

- Post-Processing

- Wafer Level

- Die Level

- Single or Few Masks

- Dedicated Process

- Prototypes

- Initial Production

- High Volume, Device Specific

- Poly MEMS

- Multi-Layer Poly

- Metal MEMS

- SOI, LIGA MEMS

- Integrated MEMS

- Multi-User, Multi-Device

- Thin Film Depositions

- Epi Growth

- Ion Implantation

- Patterning and Etch

- CMP, Dicing, Packaging

Fig. 8.1 Process architectures for MEMS devices include fully integrated processes, process vari-

ants of standard integrated circuit or MEMS processes, semicustom and fully custom processes,

standard (e.g., multidevice or multiuser) MEMS processes, and unit processes. Wet-etch sequences

may be predetermined by the selected process architecture, particularly for devices that can ﬁt into

standard and fully integrated processes. Special wet-etch sequences may require the selection of a

process variant, semicustom, fully custom, or unit process architecture

devices requiring only a few mask sequences, and for very high-volume devices.

Semicustom processes allow MEMS sequences to be placed before or more often

after an established active device (i.e., CMOS) process, providing the developer the

opportunity to select wet- or dry-etching sequences to meet speciﬁc device require-

ments. Process variants can include modiﬁcations to the etch steps to meet the

requirements f or thin-ﬁlm etching. The user of unit processes may have the strongest

say in wet process selection and execution.

A number of companies offer foundry services, comprising anywhere from sin-

gle processing steps and modules to full-blown established process ﬂows. Some of

the larger foundries offering MEMS services, subject to change, are listed in the ref-

erences [31]. For example, a user may submit a CAD design to an outside service,

which can provide multilevel metal structures on top of a variety of substrates based

on multilayer electrodeposition of materials [32]. Foundries for unit process steps

may be found through online searches or conversations with industrial experts and

foundry representatives.

Selection of a wet-etch unit process requires many considerations, some of which

are illustrated in Fig. 8.2. After development of a general process ﬂow for a partic-

ular device, etch sequences are evaluated as to whether they should be wet or dry.

462 D.W. Burns

Determine

Effectiveness

Demonstrate

Repeatability

Use Existing

Processes

Ensure

Compatibility

Evaluate

Cost

- Selectivity

- Etch Rate

- Sidewall Profile

- Inherent Overetch

- Etch Stop

- Visible End Point

- In-Line Verification

- Oxide Etch

- Dielectric Etch

- Metal Etch

- Substrate Etch

- Sacrificial Etch

- Development

- Manufacturing

- Transfer

- Maintenance

- Contamination

- Step Coverage

- PR Coverage

- Handling

- Dicing

- Packaging

Wet-Etch

Selection

Principles

Fig. 8.2 Wet-etch selection and development principles include: determine effectiveness, demon-

strate repeatability and reliability, use existing processes where possible, ensure process compati-

bility, and evaluate cost

The ﬁrst wet-etch selection principle is to determine the effectiveness of a candi-

date etchant or an etch sequence based on selectivity, etch rate, and sidewall proﬁle

requirements. The selectivity must be sufﬁciently high to etch the desired material

while having minimal impact on the masking material and any underlying ﬁlms that

become exposed as the etched material is clearing. When possible, the etch rate

should be selected to complete the etch in about 2–5 min: long enough so that inser-

tion and wetting effects are minimal, and short enough to keep the workﬂow moving

adequately and keep unit costs down. Specialized etches, s uch as sacriﬁcial etches

or anisotropic etching of substrates, may take several hours or more.

The sidewall proﬁle can be a signiﬁcant consideration when selecting a wet etch.

Wet etches, as compared to dry etches, can signiﬁcantly undercut mask features.

Fine features, such as adjacent lines and spaces, may completely disappear during

a wet etch. Undercutting also leads to broadening of device features for dark-ﬁeld

masks, affecting design rules and in some cases limiting the die size. In some situ-

ations, tapered sidewalls that generally occur with wet etches can be advantageous,

allowing better step coverage for subsequent ﬁlm deposition and patterning.

The second wet-etch selection principle is to demonstrate repeatability, reliabil-

ity, and robustness of the wet etch. For example, a ﬁnicky etch sequence requires

excessive operator attention and can ruin an entire process with even slight etch

variations. A good wet etch sequence has built-in overetch capability that allows

overetching of 5–15% or more with minimal impact on yield or device performance.

An ideal wet etch has inherent overetch capability against an etch stop and nearly

inﬁnite selectivity to other exposed materials. Highly beneﬁcial to an etch sequence

8 MEMS Wet-Etch Processes and Procedures 463

is a visible endpoint for operator-controlled etching and in-line ﬁlm-thickness ver-

iﬁcation of the etched or underlying ﬁlm, which ensures that the s elected material

has been completely removed in the targeted areas.

Wet etches are generally sensitive to etchant temperature, etchant concentration,

amount of previous use, etchant age, evaporation of the etchant or diluent in the

etchant solution, etchant loading such as the number of wafers being etched and the

percentage of exposed area including substrate backsides, feature size, ﬁlm compo-

sition, ﬁlm morphology, annealing history, surface contamination, surface residues,

incubation time, stirring or agitation, and room illumination, each requiring diligent

control for a reliable etch process.

Etches can be disqualiﬁed from consideration if the etchant is too slow; has

insufﬁcient selectivity to other masking materials and underlying layers; lacks uni-

formity; presents contamination concerns for further substrate processing; generates

unwanted compounds, residues, or pitting; causes cracks, swelling, peeling, or

excessive undercutting of the masking layer; or requires unwieldy storage, handling,

disposal, safety, and facilities concerns. Although wet etchants may offer higher

selectivity than dry etches to masking materials, they may also be appreciably more

sensitive to ﬁlm composition and annealing.

The third wet-etch selection principle is to use existing processes wherever possi-

ble. Processing facilities will generally have wet-etch capabilities for materials such

as silicon dioxide and metals such as aluminum that can be adapted as needed to

the particular ﬁlm thickness of interest. Dedicated stations may be available for par-

ticular processes such as anisotropic etching of substrates. Where special etches are

required, such as an extensive sacriﬁcial etch, it is wise to adapt existing processes

and equipment only as needed to achieve the desired etch characteristics. Those who

have developed a customized etch to fabricate a device know the signiﬁcant amount

of time and effort required to develop, characterize, and qualify the specialized etch.

The fourth wet-etch principle is to ensure compatibility with other aspects of

the device process and the facility where the device is to be developed. Cross-

contamination into other devices, equipment, and processes via wafer routing or

wafer handling in common holders and etch baths can unexpectedly have a detri-

mental impact on other devices. The developer needs to ensure that subsequent

sequences within a given device process are compatible, considering step cover-

age for subsequent deposition steps and photoresist spinning, the handling of fragile

devices, dicing requirements, and packaging needs.

When multiple options exist after due consideration has been given to the above

principles for wet-etch selection, the next step is to consider all the costs of develop-

ment, manufacturing and technology transfer, equipment and facility maintenance,

and the overhead associated with ﬂoor space, process controls, and supplies. Costs

are generally lowest when existing processes within a facility are used, because the

expense for etching with an existing process is usually marginal or incremental and

does not require additional capitalization or development efforts.

Those who have developed or are currently developing a semiconductor or

MEMS device recognize the extensive interplay between process sequences and

device design. If the etch sequence cannot be adjusted to achieve the desired result,