Becker W. Advanced Time-Correlated Single Photon Counting Techniques

Подождите немного. Документ загружается.

44 3 Multidimensional TCSPC Techniques

of relatively moderate count rate. Therefore the FIFO has to be large enough to

buffer the photon data for a sufficient time. In practice FIFO sizes of 64,000 to 8

million photons are used.

The macro time clock can be started by an external experiment trigger or by a

start-measurement command from the operating software. In some TCSPC mod-

ules the clock signal source of the macro time clock can be selected. The macro

time clock can be an internal quartz oscillator, an external clock source, or the

reference signal from the laser. Triggering and external clock synchronisation are

absolute requirements for multimodule operation in the time-tag mode, see

Sect. 5.11.3, page 189.

In principle, many multidimensional recording problems can also be solved in

the time-tag mode. Synchronisation with the experiment can be accomplished via

the experiment trigger, the macro time clock, and additional experiment control

bits read into the channel register. The drawback of the time-tag mode is the large

amount of data that has to be transferred into the computer and processed or

stored. A single photon typically consumes four or six bytes. A single FLIM or

DOT recording may deliver 10

to 10

photons, resulting in several gigabytes of

data. At high count rates the bus transfer rate into the computer may be still suffi-

cient, but the computer may be unable to process the data on-line or to write them

to the hard disc. The transfer rate problem is even more severe for multimodule

systems. Nevertheless, the time-tag mode is sometimes used for imaging and for

standard fluorescence lifetime experiments. This is not objectionable as long as

the system takes into account possible count rate limitations by the bus transfer

rate, as well as the enormous file sizes and possible synchronisation problems.

Time-tag recording is used in fluorescence correlation spectroscopy (FCS) [51,

335, 368, 429], fluorescence intensity distribution analysis (FIDA), and time-

resolved single molecule spectroscopy by burst-integrated fluorescence lifetime

(BIFL) detection [155, 419]. FCS records the autocorrelation and cross-correlation

functions of the fluorescence intensity. FIDA builds up histograms of the photon

numbers in subsequent sampling time intervals. In both cases the fluorescence life-

time yields additional information about different fluorescent species in the sample.

BIFL detects the fluorescence bursts of single molecules and analyses the fluores-

cence lifetime and anisotropy in the bursts, the burst duration, and the times between

the bursts. The techniques are described under Sect. 5.10, Sect. 5.12, and Sect. 5.13,

page 193.

The time-tag mode in conjunction with multidetector capability and MHz

counting capability was introduced in 1996 with the SPC431 and SPC432 mod-

ules of Becker & Hickl. Its large potential in single molecule spectroscopy began

to attract attention when sufficiently fast computers with large memories and hard

discs became available.

3.7 Multimodule Systems 45

3.7 Multimodule Systems

The maximum count rate of a single TCSPC channel is limited not only by the

counting loss due to the „dead time“ of the TCSPC channel, but also by pile-up

effects and the counting capability of the detector.

Compared with classic systems, the dead time of advanced TCSPC systems has

been considerably reduced. It is however, still on the order of 100 to 150 ns. The

fraction of photons lost in the dead time – the „counting loss“ - becomes notice-

able at detector count rates higher than 10% of the reciprocal dead time (see

Sect. 7.9.2, page 338). The counting loss can be compensated for by a dead-time-

compensated acquisition time. Therefore, often a relatively high loss can be toler-

ated. The practical limit is the „maximum useful“ count rate, which is defined as

the recorded rate at which 50% of the photons are lost. For currently available

TCSPC modules, the maximum useful count rate ranges from 3 to 5 MHz, corre-

sponding to a detector count rate from 6 to 10 MHz.

Pile-up is caused by the detection of a second photon within one signal period

[104, 105, 238, 389, 549]. Because a second photon is more likely to be detected

in the later part of a signal period, pile-up causes a distortion of the signal shape

(see Sect. 7.9.1, page 332). The pile-up distortion is smaller than commonly be-

lieved (see Fig. 7.78, page 336), and reasonable results can be obtained up to a

detector count rate of 10 to 20% of the signal repetition rate. Nevertheless, the

pile-up sets a limit to the applicable count rate.

The third limitation, the counting capability of the detector, depends on the de-

tector type used, the voltage divider design, and the requirements for IRF stability,

long-term gain stability, and detector lifetime. For conventional PMTs the practi-

cal limit for TCSPC is of the order of 5 to 10 MHz. For MCP-PMTs the maximum

count rate is 200 kHz to 2 MHz, depending on the MCP gain used.

Because of pile-up and detector effects, a breakthrough in the counting capabil-

ity of TCSPC cannot be achieved by simply making the signal processing elec-

tronics of the TCSPC device faster.

The only solution to the count rate problem is multimodule operation. Splitting

the light into several detectors connected to independent TCSPC modules propor-

tionally increases the counting capability. Of course, multimodule operation also

increases the system cost and can cause space and power supply problems in the

host computer. These problems have at least partially been solved since packages

of relatively small and cost-efficient TCSPC modules are available. A fully paral-

lel four-channel package (SPC134, Becker & Hickl, Berlin) is shown in

Fig. 3.16.

46 3 Multidimensional TCSPC Techniques

Fig. 3.16 Package of four fully parallel TCSPC channels

With a dead time of 100 ns per TCSPC channel, total useful count rates of the

order of 20 MHz can be achieved. All four channels can be used for multidetector

operation. The high count rate and the high number of channels make multimod-

ule TCSPC systems exceptionally useful for diffuse optical tomography [34], and

high count rate applications in laser scanning microscopy [39]. Details are de-

scribed under Sect. 5.5, page 97 and Sect. 5.7, page 129.

Another application of multimodule systems is in correlation spectroscopy of

single molecules. If the photons detected in different detectors are recorded in

different modules, the minimum correlation time is no longer limited by the dead

time. By synchronising the macrotime clocks of the modules, a continuous corre-

lation from the picosecond to the millisecond scale can be achieved, see

Sect. 5.11.3, page 189.

4 Building Blocks of Advanced TCSPC Devices

4.1 Constant-Fraction Discriminators

TCSPC is based on the measurement of the detection times of individual photons

of the detected light signal. Accurate time measurement means accurate triggering

on the single-photon pulses of the detector and the reference pulses from the light

source. Unfortunately, the pulses at both inputs are far from being stable. The

single-photon pulses have a considerable amplitude jitter due to the random ampli-

fication mechanism in the detector, and the reference pulse amplitude may change

due to intensity fluctuations of the light source.

Of course, a simple leading edge discriminator cannot be used to trigger on

such pulses. The amplitude jitter would introduce a timing jitter of the order of the

pulse rise time (Fig. 4.1, left). In practice the timing jitter is even larger because

any discriminator has an intrinsic delay that depends on the signal slope speed and

the amount of overdrive.

Zero Cross Point is

Independent of Amplitude

Input Pulse

Delayed Pulse

Difference

Input Pulse

Threshold

Timing Jitter

Trigger

Fig. 4.1 Leading edge triggering (left) and constant fraction (zero cross) triggering (right)

Therefore constant-fraction discriminators (CFDs) are used both at the detector

and at the reference input. The CFD triggers at a constant fraction of the pulse

amplitude, thus avoiding pulse-height-induced timing jitter. Early CFD implemen-

tations used tunnel diodes as trigger elements [181, 317, 348]. CFD design was

considerably simplified with the introduction of fast comparator chips (AM 685,

AD 96685, SPT9689) based on ECL (Emitter Coupled Logic) [264, 467].

48 4 Building Blocks of Advanced TCSPC Devices

The new CFDs use the differential inputs of the comparators to trigger at the base-

line transition between the difference of the input pulse and a delayed pulse

(Fig. 4.1, right).

Theoretically the temporal position of the baseline-cross point is independent of

the pulse amplitude. In practice there is a residual jitter due to the dependence of

the intrinsic delay of the discriminator on the slope speed and the amount of over-

drive. The residual jitter can be minimised by selecting a trigger threshold slightly

different from zero.

In practice, direct triggering at a signal level of exactly zero is impossible. Ul-

trafast discriminators tend to oscillate at zero input voltage, and the smallest noise

amplitudes outside a PMT pulse cause the discriminator to trigger. Therefore,

practical implementations of the principle use a combination of a leading edge

discriminator and a zero cross trigger. The principle is shown in Fig. 4.2.

Zero Cross Level

DEL1

Input Difference

Voltage:

DEL2

D-FF

Clk

res

Threshold

Reset

Differential

Output

Pulses

Input

Fig. 4.2 Constant fraction discriminator using zero cross triggering

The comparator of the leading edge discriminator, C1, is connected directly to

the input and responds when the input voltage exceeds a defined threshold.

The zero cross trigger, C2, gets its input signals via two passive delay lines,

DEL1 and DEL2. The effective input signal is the difference of the pulses at the

input and the output of DEL2. At the baseline transition of the difference voltage

C2 triggers and produces a positive transition at its output. This pulse is used as a

clock input of a fast ECL D-flip-flop. A D-flip-flop stores the information at the

D input with the active edge of the signal at the clock input. The D input comes

from the leading edge discriminator. Therefore the flip-flop is set if a baseline

cross is detected during the time when the input voltage is above the threshold of

the leading edge discriminator. After the circuit has triggered the D-flip-flop is

reset either externally or via an additional logic gate.

The effective shape of the zero cross can be optimised by changing DEL2 and

by changing R1 and R2. DEL1 is selected to place the pulse edge of C2 within the

pulse delivered by C1.

In practice the timing accuracy depends on the speed of the discriminators and

the D-flip-flop. The discriminators have to respond to very short pulses down to

4.1 Constant-Fraction Discriminators 49

500 ps duration, and the change of the intrinsic delay due to pulse amplitude varia-

tions must be as small as possible. The D-flip-flop has to pick off the transition at

the clock input within the duration of the signal at the D input. Although both

signals can be as short as 1 ns, the delay must be independent of the previous state

of the D and clock lines.

In most TCSPC modules, rate counters complement the CFDs in the photon

pulse and reference channels of TCSPC devices. The CFDs of the photon channel

and the reference channel are often different. The photon channel is designed for

lowest amplitude-induced timing jitter and the reference channel for highest trig-

ger rate. Some TCSPC devices do not use a CFD in the reference channel at all

and rely instead on the stability of the reference pulses.

An interesting feature can be added by placing a selectable frequency divider

behind the CFD of the reference channel. The effect of the frequency divider is

shown in Fig. 4.3.

Reference

Reference / 4

Light Signal

Recorded

Photon

Distribution

Time Measurement

(Ecxitation)

Fig. 4.3 Frequency divider in the reference path of the reversed-start-stop configuration.

With an n-to-1 divider n signal periods are recorded

The frequency divider delivers a stop pulse to the TAC in each n-th signal period.

The time of a photon detected anywhere within these n periods is measured against

this stop pulse. Consequently, the photon distribution builds up over n periods.

Recording several signal periods may be considered useless at first glance. The

reduced effective stop rate increases pile-up effects at high count rates, and com-

mon data analysis processes exploit only one signal period. Nevertheless, the

reference frequency divider is useful to locate the signal pulse within a larger

conversion window of the TAC / ADC combination. The most important applica-

tion of the reference divider is the calibration of the time scale of a TCSPC sys-

tem. When several signal periods are recorded, the pulse period of the signal can

be used as a reference for the time scale (see Fig. 7.88, page 346). The pulse pe-

riod is determined either by the cavity length of the laser or by the quartz oscilla-

tor of a diode laser. In either case it is stable and known with high precision. Any-

one who has attempted to calibrate the time scale of a TCSPC system using optical

delay lines or a „known“ fluorescence lifetime can confirm the simplicity and

accuracy of a calibration based on the pulse period.

50 4 Building Blocks of Advanced TCSPC Devices

4.2 Time Measurement Block

There are a number of different time measurement techniques applicable to

TCSPC. The TAC-ADC principle of the classic TCSPC technique has been up-

graded with a fast, error-cancelling ADC technique. Integrated circuits for direct

time-to digital conversion (TDCs) have been developed, and a sine-wave time-

conversion technique has been introduced.

4.2.1 Time Measurement by Fast TAC / ADC Principle

Because of its superior time resolution the conventional TAC-ADC technique

used in the classic TCSPC setups is still used in advanced TCSPC devices. How-

ever, the conventional TAC-ADC technique has been upgraded by a modified

ADC principle that cancels the nonuniformity of the ADC characteristics. With

the new ADC technique, ADC chips with moderate accuracy but extremely high

speed can be used. Together with a speed-optimised TAC circuitry, the new ADC

technique achieves exceptionally high conversion rates.

TAC

The general principle of a TAC is shown in Fig. 4.4. The circuit contains two flip-

flops, FF1 and FF2, controlling two switches, S1 and S2. In the quiescent state

both switches are in the „0“ position. The current of a current source, I

, flows

through S1 and S2 into ground. The voltage at the timing capacitor, C, is zero. A

start pulse sets FF1 which switches S1 into the „1“ position. The current I

now

flows into the timing capacitor, causing a linearly increasing voltage across it. The

stop pulse sets FF2, which switches S2 into the „1“ position. The switch diverts I

into ground, and the voltage across C remains constant at a level proportional to

the time difference between start and stop. When the voltage at C has been sam-

pled by a subsequent ADC, both flip-flops are reset so that the voltage across C

returns to zero.

FF 2

FF 1

reset

Start

Stop

Start

Stop

reset

Vcc

Fig. 4.4 General principle of a time-to-amplitude converter

4.2 Time Measurement Block 51

To obtain a high differential linearity of a TAC two points are essential: a fully

differential design, minimising crosstalk between the start and stop signals, and

switches with low switching transients. A practical implementation is shown in

Fig. 4.5.

Clk

res

/Clk

Clk

res

/Clk

Current Feedback

Vcc

Vee

'1'

reset

stop

/stop

start

/start

Vout

Differential Clock

D Flip-Flop

Differential Clock

D Flip-Flop

Buffer Amplifier

FF1

FF2

AMP1

Offset

Variable Gain

Limiting Amplifier

Rfb

Vdith

AMP2

I > Is

Level

Shifter

Level

Shifter

Fig. 4.5 Practical implementation of the TAC principle

The flip-flops, FF1 and FF2, are fast ECL logic differential clock D-flip flops.

The switches, S1 and S2, are formed by transistor pairs, Q1, Q2, and Q4, Q5. The

current source is Q6. In the quiescent state Q2 and Q5 are conducting. I

flows

through Q5 and Q2. Q2 drains a current, I

, which is held higher than I

. The

difference, I

– I

, flows through the Schottky diode, D, which provides a stable

quiescent voltage, V

, at the timing capacitor, C. When FF1 is started by a start

pulse I

is diverted through Q1 into ground and I

flows into C, causing V

increase linearly. A stop pulse sets FF2 diverting also I

into ground. Now, the

voltage across C remains constant until a reset pulse switches both flip-flops into

the quiescent state. Vc is buffered by an amplifier, AMP1, which is usually a cur-

rent feedback amplifier of low input current. The buffered voltage is amplified by

the TAC output amplifier, AMP2. This amplifier has a variable gain and a variable

offset, and limits the signal to the range of the subsequent ADC. By changing the

gain and the offset of AMP2 subranges within the conversion range of the TAC

core can be defined. Furthermore, there is an input to add the „dither“ voltage,

Vdith, which is used for ADC error cancellation (see below).

In the circuit principle shown in Fig. 4.5 all start and stop related signals are

fully differential, resulting in minimum crosstalk between start and stop. Further-

more, the voltage across the current source of I

does not change with the switch-

ing operation and the output impedance of Q2 and Q5 remains high up to very

high frequencies. Ringing of I

and other switching transients is therefore mini-

mised.

In practice a TAC circuit contains additional circuitry that generates a start

pulse for a subsequent ADC, resets FF1 and FF2 after the ADC has sampled the

52 4 Building Blocks of Advanced TCSPC Devices

TAC output voltage, and keeps the TAC in the reset state until the timing capaci-

tor is completely discharged. The time scale can be changed by electronically

switching different capacitors, C, to the output of Q2 and Q5, and by controlling

the charge current, I

. The TAC can also contain discriminators which inhibit the

start of the ADC if the TAC output voltage, Vout, is outside the conversion range

of the subsequent ADC.

The TAC module of a Becker & Hickl SPC830 TCSPC device is shown in

Fig. 4.6. The module is built in chip-and-wire hybrid technique. Most of the semi-

conductor chips are inserted as bare dice connected to the signal lines on the sub-

strate by bond wires.

Fig. 4.6 TAC in hybrid technique (approximately life size)

Fast ADC with Error Correction

The ADC of a TCSPC system has to work with an extremely high accuracy. It has

to resolve the TAC signal into several thousand time channels, and the width of

the particular channels must be equal within 1% or better. ADC chips are usually

specified by a „nonmissing code accuracy“ which defines the number of bits for

which the ADC characteristics is still monotonous. 12-bit conversion with a chan-

nel uniformity of 1% requires a nonmissing code accuracy of 19 bits. Although

ADCs with such a high accuracy exist, they are far too slow for TCSPC applica-

tions. Therefore, in the early TCSPC systems, the ADC was the bottleneck both in

terms of speed and channel uniformity [383].

A breakthrough was achieved by an error correction technique based on a

modified „dithering“ process [29, 34]. Dithering is a technique to enhance the

resolution of an ADC by accumulating a large number of samples with a digitally

generated noise (the dither signal) added to the input signal. The digital equivalent

of the dither signal is later subtracted from the ADC output bytes.

In TCSPC the principle of dithering is reversed. The ADC input signal is ran-

dom, and a determinate dither signal is used. The principle is shown in Fig. 4.7.

4.2 Time Measurement Block 53

CNT

START

STOP

Address

Vdith

Var. Gain

Amplifier

Offset

Vout

TAC Core

ADC

DAC

Counter

= Vc+Vdith

ADW

CNT

ADW-CNT

Time of Photon

Memory

AMP2

TAC

TIME =

Fig. 4.7 ADC error correction technique

The basic idea is to give the TAC characteristic a variable offset referred to the

ADC characteristic. Thus photons are converted at slightly different positions on the

ADC characteristic, even if they are detected at the same time in the signal periods.

A digital-to-analog converter, DAC, is used to shift the TAC output voltage up

and down on the ADC characteristics. This „dither“ DAC is controlled by a

counter that counts the start pulses of the TAC. Consequently the dither DAC

generates a sawtooth voltage, Vdith, that increases by one DAC step at the re-

cording of each photon. The DAC voltage is added to the output voltage of the

TAC core, Vc. The resulting signal, V

out

= V

+ V

dith

, is converted by the ADC. To

restore the correct time of the photon the counter output word, CNT, i.e. the digital

expression of V

dith

, is digitally subtracted from the ADC word, ADW. The result is

used to address the memory in which the photon distribution is built up.

Of course, a single address byte still contains the unavoidable deviation of the

particular ADC step from the correct value. But there is a significant difference

from a direct ADC conversion in that the error is now different for different pho-

tons. Because a large number of photons are collected the errors are averaged. The

result is a smoothing of the effective ADC characteristic.

For an ideal dither DAC, the smoothing of the ADC characteristics does not

cause any loss of signal detail. In practice, gain and linearity errors of the DAC

cause a slight broadening of the recorded signal of the order of 1 or 2 ADC steps.

The improvement in conversion accuracy depends on the number of ADC

steps, N

dac

, over which the signal is dithered, and on the distribution of the errors

of the ADC characteristic. If the size of an ADC step has no correlation to the size

of the adjacent steps the improvement is N

dac

1/2

. In practice the design principle

used in ultrafast ADC chips results in more or less periodic errors. In this case the

improvement in accuracy is considerably higher than N

dac

1/2

Figure 4.8 shows the differential nonlinearity (left) and the electronic instru-

ment response function (right) of an SPC134 TCSPC module (Becker & Hickl,

Berlin) for a different number of DAC bits, Ndac. The nonlinearity curves were

recorded by detecting a continuous, unmodulated light signal. The instrument

response functions were measured by using 1 ns pulses from a pulse generator at

the photon pulse and reference inputs.