Alciatore D.G., Histand M.B. Introduction to Mechatronics and Measurement Systems

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6.2 Digital Representations 201

Another base useful in representing binary numbers in concise form is octal

(base 8). To convert a binary number to octal, divide the number into groups of three

digits beginning with the least significant bit and replace each group with its octal

equivalent. For example,

123

001 111 011

173

(6.7)

Table 6.2 Hexadecimal symbols and equivalents

Binary Hexadecimal Decimal

0000 0 0

0001 1 1

0010 2 2

0011 3 3

0100 4 4

0101 5 5

0110 6 6

0111 7 7

1000 8 8

1001 9 9

1010 A 10

1011 B 11

1100 C 12

1101 D 13

1110 E 14

1111 F 15

■ CLASS DISCUSSION ITEM 6.1

Nerd Numbers

Why do geeky engineers sometimes confuse Halloween (OCT 31) and Christmas

(DEC 25)?

In addition to numbers, alphanumeric characters can also be represented in digi-

tal (binary) form with ASCII codes. ASCII is short for the A merican S tandard C ode

for I nformation I nterchange. ASCII codes are 7-bit codes used to denote all of the

alphanumeric characters. The 7-bit codes are usually stored in an 8-bit byte. There is

a unique code for each alphanumeric character. Some example codes are

A: 0100 0001  41

 65

B: 0100 0010  42

 66

0: 0011 0000  30

 48

1: 0011 0001  31

 49

The complete set of ASCII codes can be found at Internet Link 6.1.

Internet Lin

6.1ASCII codes

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202 CHAPTER 6 Digital Circuits

Binary coded decimal (BCD) is another type of digital representation some-

times used for input and output of numerical data. With BCD, 4 bits are used to

represent a single, base 10 digit. BCD is a convenient mechanism for representing

decimal numbers in a binary number format, but it is inefficient for storing or trans-

mitting multiple-digit numbers because only 10 of the 16 (2

) possible states of the

4-bit number are used. To convert a decimal number to BCD, assemble the 4-bit

codes for each decimal digit. For example,

123

0001 0010 0011

bcd

(6.8)

Note that this is different from the binary representation:

0111 1011

(6.9)

■ CLASS DISCUSSION ITEM 6.2

Computer Magic

How can a digital computer perform the complex operations it does given that its

architecture and operation are based on simply manipulating bits (zeros and ones)?

6.3 COMBINATIONAL LOGIC

AND LOGIC CLASSES

Combinational logic devices are digital devices that convert binary inputs into binary

outputs based on the rules of mathematical logic. The basic operations, schematic

symbols, and algebraic expressions for combinational logic devices are shown in

Table 6.3 . These devices are also called gates, because they control the flow of sig-

nals from the inputs to the single output. A small circle at the input or output of a

digital device denotes signal inversion; that is, a 0 becomes a 1 or a 1 becomes a 0.

For example, the NAND and NOR gates are AND and OR gates, respectively, with

the output inverted, hence the circle is shown on the output. The truth table for each

device is shown on the right. The truth table is a compact means of displaying all

combinations of inputs and their corresponding outputs. Usually the combination of

inputs is written as the ascending list of binary numbers whose number of bits corre-

sponds to the number of inputs (e.g., 00, 01, 10, 11 for two inputs). Internet Link 6.2

provides a fun online digital circuit simulator allowing you to drag-and-drop and

connect logic gates in different ways to interactively see how combinational logic

circuits function.

The standard AND, NAND, OR, NOR, and XOR gates have only two inputs,

but other forms are available with more than two inputs. In the case of a multiple

input AND gate, the output is 1 if and only if all inputs are 1; otherwise, the output is

0. In the case of the OR gate, the output is 0 if and only if all inputs are 0; otherwise,

it is 1. In the case of the XOR gate, the output is 0 if all of the inputs are 0 or if all of

Internet Lin

6.2“Logicly”

combinational

logic online

simulator

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6.3 Combinational Logic and Logic Classes 203

Table 6.3 Combinational logic operations

Gate Operation Symbol Expression Truth Table

Inverter

(INV, NOT)

Invert signal

(complement)

C  A A C

0 1

1 0

AND gate AND logic

C  A · B A B C

0 0 0

0 1 0

1 0 0

1 1 1

NAND gate Inverted AND

logic

C  A · B A B C

0 0 1

0 1 1

1 0 1

1 1 0

OR gate OR logic

C  A  B A B C

0 0 0

0 1 1

1 0 1

1 1 1

NOR gate Inverted OR

logic

C  A  B A B C

0 0 1

0 1 0

1 0 0

1 1 0

XOR gate Exclusive OR

logic

C  A ⊕ B

 A · B  A · B

A B C

0 0 0

0 1 1

1 0 1

1 1 0

Buffer Increase output

signal current

C  A A C

0 0

1 1

the inputs are 1; otherwise, it is 1. The algebraic symbols used to represent the logic

functions are: plus (  ) for logic OR, dot (·) for the logic AND, and an overbar (  )

for logic NOT, denoting inversion.

A buffer is used to increase the current supplied at the output while retain-

ing the digital state. This is important if you wish to drive multiple digital inputs

from a single output. A normal digital gate has a limited fan-out, which defines the

maximum number of similar digital inputs that can be driven by the gate’s output

(see Section 6.11.3 ). The buffer overcomes fan-out limitations by providing more

output current.

Video Demo

5.1Integrated

circuits

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204 CHAPTER 6 Digital Circuits

All the gates in Table 6.3 are manufactured as integrated circuits where transis-

tors, resistors, and diodes exist on a single chip of silicon. Video Demo 5.1 shows

various types of IC packages, and Video Demos 5.2 through 5.4 describe and illus-

trate all of the steps of the IC manufacturing process.

There are two families of digital integrated circuits, called TTL for transistor-

transistor logic and CMOS for complementary metal-oxide semiconductors. Voltage

levels define logic low (0) and logic high (1) at the inputs and outputs. The ranges

for the logic levels vary depending on the device family. A designer must be careful

when mixing different types of digital integrated circuits because different digital

devices have specified current source and sink capabilities that affect how much fan-

out is allowed and how they may be mixed with each other. The TTL and CMOS

families are described in detail in Section 6.11.

This example illustrates how to determine signal expressions and values in a logic diagram.

Here is an example logic circuit:

ABC

Signals A, B, and C are inputs and signals D, E, and F are outputs. Each of the signals

can be high (1) or low (0). When analyzing a logic circuit, start by writing out logic expres-

sions for all signals in the circuit. D is the most straightforward because it is simply the AND

combination of signals A and B:

DAB⋅=

Signal E depends on signal D and uses the circle inversion symbol on the C input to the OR

gate, so

This can also be written as

EAB⋅

()

C+=

Finally, signal F is the result of a NAND combination of signal E and the inverse of C:

FEC⋅=

Note that the inversion bar goes over the entire expression E · C because the NAND gate

inverts the output of the AND combination of E and C.

Combinational Logic

EXAMPLE 6.2

Video Demo

5.2Integrated

circuit

manufacturing

process stages

5.3Chip

manufacturing

process

5.4How a CPU is

made

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6.4 Timing Diagrams 205

Another way to express the functionality of the logic circuit is to summarize all the

possible input and output combinations in a truth table as follows. Each output value can be

determined from the logic expressions. For example, for input combination A  0, B  0, and

C  0, D  0 · 0  0, E  0  0  0  1  1, F  1 · 0  1 · 1  1  0.

ABCDEF

000010

001001

010010

011001

100010

101001

110110

111111

When you become comfortable with logic expressions and truth tables, you will be

able to construct the table very quickly using some short-cuts. For example, because D is the

AND combination of A and B, D is 1 only if A is 1 and B is 1; otherwise, D is 0. Therefore,

you can quickly fill in column D with all zeros except where A and B are both 1. Likewise,

with column E, which is an OR combination, the output is 1 if D is 1 or i f C is 1 (i.e., C is 0).

Another way to interpret this is that E is 0 only if both D is 0 and C is 0 (i.e., C is 1). F is 0

(1 inverted) if E is 1 and C is 1 (i.e., C is 0).

6.4 TIMING DIAGRAMS

In order to analyze complex logic circuits it helps to sketch a timing diagram, which

shows the simultaneous levels of the inputs and outputs in a circuit vs. time. The

timing diagram can be used to illustrate every possible combination of input values

and corresponding outputs, providing a graphical summary of the input/output rela-

tionships. Timing diagrams for the AND and OR gates are shown in Figures 6.2 and

6.3 as examples. Multiple-input digital oscilloscopes and logic analyzers have the

capability to display timing diagrams for digital circuits.

Figure 6.2 AND gate timing diagram.

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Figure 6.3 OR gate timing diagram.

206 CHAPTER 6 Digital Circuits

6.5 BOOLEAN ALGEBRA

In formulating mathematical expressions for logic circuits, it is important to have

knowledge of Boolean algebra, which defines the rules for expressing and simpli-

fying binary logic statements. The basic Boolean laws and identities follow. A bar

over a symbol indicates the Boolean operation NOT, which corresponds to inversion

of a signal.

Boolean Algebra Laws and Identities

Fundamental Laws

OR AND NOT

A + 0 = AA · 0 = 0

A + 1 = 1 A · 1 = A

A + A = A A · A = A

A + = 1 A · = 0

(double inversion)

AA=

A A

(6.10)

Commutative Laws

AB+ BA+=

(6.11)

AB⋅ BA⋅=

(6.12)

Associative Laws

AB+

()

C+ ABC+

()

(6.13)

AB⋅()C⋅ ABC⋅()⋅=

(6.14)

Distributive Laws

ABC+()⋅ AB⋅()AC⋅()+=

(6.15)

BC⋅()+ AB+()AC+()⋅=

(6.16)

Other Useful Identities

AAB⋅

()

+ A=

(6.17)

AAB+()⋅ A=

(6.18)

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6.5 Boolean Algebra 207

AAB⋅

()

+ AB+=

(6.19)

AB+()AB+()⋅ A=

(6.20)

AB+()AC+()⋅ ABC⋅(

)

(6.21)

AB AB⋅()++ AB+=

(6.22)

AB⋅()BC⋅()BC⋅()++ AB⋅()C+=

(6.23)

AB⋅()AC⋅()BC⋅()++ AB⋅()BC⋅()+=

(6.24)

De Morgan’s laws are also useful in rearranging or simplifying longer Boolean

expressions or in converting between AND and OR gates:

ABC· · ·+++ ABC · · ·⋅⋅⋅=

(6.25)

BC· · ·⋅⋅⋅ ABC· · ·+++=

(6.26)

If we invert both sides of these equations and apply the double NOT law from Equa-

tion 6.10 , we can write De Morgan’s laws in the alternative form:

ABC· · ·+++ ABC· · ·⋅⋅⋅=

(6.27)

ABC· · ·⋅⋅⋅ ABC· · ·+++=

(6.28)

Truth tables can be very helpful in verifying an identity. For example, to show

that Equation 6.19 is valid, we can construct the following truth table where each

term in the identity is evaluated for all input combinations:

A ABA · B (A  A · B A  B

100 0 1 1

101 0 1 1

010 0 0 0

011 1 1 1

Because both sides of the identity are equal for every input combination, the identity

is valid.

Simplifying a Boolean Expression

EXAMPLE 6.3

Simplify the following expression using Boolean laws and identities:

X ABC⋅⋅()BC⋅()AB⋅()++=

First, we can rewrite this equation using the associative law and the fundamental law that

Z · 1  Z:

XABC⋅()1+ BC⋅()AB⋅()+⋅⋅=

(continued )

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208 CHAPTER 6 Digital Circuits

In this form, it is clear that we can use the distributive law to factor out the ( B · C ) term:

XA1+()BC⋅()⋅ AB⋅()+=

Because A  1  1 and 1 · ( B · C )  B · C,

XBC⋅()AB⋅()+=

Furthermore, using the associative and distributive laws we can factor out B:

XBCA+()⋅=

We have reduced the number of operators from seven in the original expression (including

the inversion) to three in the final expression. This is important because it reduces the number

of gates required to build the circuit.

(continued )

6.6 DESIGN OF LOGIC NETWORKS

As an example illustrating the application of combinational logic to a real engineer-

ing problem, suppose you are asked to design a circuit for a simple security pro-

tection system for a home. The homeowner wants an alarm to sound if someone

breaks into the house through a door or window or if something is moving around

in the house while the occupants are away. Under certain conditions, the users may

also want to disable portions of the alarm system. We assume that there are sensors

to detect if windows or doors are disturbed and to detect motion. To accomplish

the goals of this security system, we design a combinational logic circuit using two

switches that can be set by the owner.

The following steps facilitate the design of a digital circuit to solve this type of

problem:

1 . Define the problem in words.

2 . Write quasi-logic statements in English that can be translated into Boolean

expressions.

3 . Write the Boolean expressions.

4 . Simplify and optimize the Boolean expressions, if possible.

5 . Write an all-AND, all-NAND, all-OR, or all-NOR realization of the circuit to

minimize the number of required logic gate IC components.

6 . Draw the logic schematic for the electronic realization of the circuit.

Each of these steps is carried out for the security lock example in the following

sections.

6.6.1 Define the Problem in Words

We begin our logic design by translating the problem into a series of word state-

ments that reflect what should be happening in the system. We want the alarm sys-

tem to create a high signal, sounding the alarm for certain combinations of the

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6.6 Design of Logic Networks 209

house sensors. Also, we want the user to be able to select one of three operating

states:

1 . An active state where the alarm will sound only if the windows or doors are

disturbed. This state is useful when the occupants are sleeping.

2 . An active state where the alarm will sound if the windows or doors are disturbed

or if there is motion in the house. This state is useful when the occupants are

away.

3 . A disabled state where the alarm will not sound. This state is useful during

normal household activity.

At this time, we must define Boolean variables that will represent the inputs

and outputs of the circuit. The following Boolean variables are used to design the

security system logic:

■ A: state of the door and window sensors

■ B: state of the motion detector

■ Y: output used to sound the alarm

■ C D: 2-bit code set by the user to select the operating state defined by

0 1 operating state 1

1 0 operating state 2

0 0 operating state 3

⎩

⎪

⎨

⎪

⎧

The inputs to the system are A, B, C, and D, and the output is Y. We assume positive

logic for A, B, and Y, where a 1 implies active or ON and a 0 implies inactive or OFF.

6.6.2 Write Quasi-Logic Statements

We further translate the word statements into logic-like statements. The quasi-logic

statements for the security system are

Activate the alarm ( Y  1) if A is high and the code C D is 0 1 or activate the alarm if

A or B is high and the code is 1 0.

Note the italicized quasi-Boolean operators, which should aid in writing the Boolean

expression.

6.6.3 Write the Boolean Expression

Now we write the Boolean expression based on the quasi-logic statement. To create a

product of 1 for the active control code 0 1, we need to form the expression C · D; to

create a product of 1 for the other active control code 1 0, we need to form the expres-

sion C · D. Based on this, the complete Boolean expression for the security system is

YACD⋅()⋅ AB+()CD⋅()⋅+=

(6.29)

The alarm will sound ( Y  1) if the expression A · (C · D) is 1 or if the expres-

sion (A  B) · (C · D) is 1; otherwise, the alarm will not sound ( Y  0). The first

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210 CHAPTER 6 Digital Circuits

expression will be 1 if and only if A is 1 and C is 0 and D is 1; the second expression

will be 1 if and only if A or B is 1 and C is 1 and D is 0.

For this particular problem, we can simplify Equation 6.29 by looking at a truth

table for the C and D terms for the different control code combinations.

CD(C · D) (C · D)

00 0 0

10 0 1

01 1 0

Note that (C · D)  D and (C · D)  C for the given control code combinations. If we

disallow the state C D  1 1 (see Question 6.21 ), Equation 6.29 can be simplified as

YAD⋅()AB+()C⋅+=

(6.30)

6.6.4 AND Realization

Once a Boolean expression is simplified, it may be desirable to manipulate the result

further in order to convert all operations to a preferred type of gate (e.g., AND or

OR). The reason for this is that logic gates come packaged on integrated circuits

(logic ICs) in groups of four, six, or eight. Therefore, we may be able to reduce the

total number of ICs required by using all of one type of gate. Converting from one

gate type to another is easily accomplished with a repeated application of De Mor-

gan’s laws. For the security system example, an all-AND representation is achieved

by applying Equation 6.27 to convert each OR gate to an AND gate. Starting with

Equation 6.30 :

YAD⋅

()

AB+

()

C⋅+=

(6.31)

First, we convert the second OR gate expression A  B:

YAD⋅()AB⋅()C⋅+=

(6.32)

Now we have one expression OR-ed into another. Again, Equation 6.30 states that

to convert the OR gate to an AND gate, invert each expression, change the gate, and

invert the whole expression:

YAD⋅ AB⋅

()

C⋅⋅=

(6.33)

6.6.5 Draw the Circuit Diagram

Now it is relatively straightforward to draw the circuit using only AND gates and

inverters from inspection of the final Boolean expression in Equation 6.33 , by build-

ing the subexpressions one at a time and connecting them as shown in Figure 6.4 .

It is a good idea to label intermediate signals in a logic circuit with their corre-

sponding Boolean expressions, as shown. This will help you prevent or find errors in

your logic.

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