Alciatore D.G., Histand M.B. Introduction to Mechatronics and Measurement Systems

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Figure 6.15 Positive edge-triggered T flip-flop.

Preset

Clear

Preset

Clear

6.9 Flip-Flops 221

Table 6.9 Positive edge-triggered T flip-flop truth table

T Preset Clear QQ

↑

011

111

X0110

X1001

Given the following sequential logic circuit that includes RS, T, and JK flip-flops with the

inputs as indicated in the timing diagram, the digital outputs D, E, and F will be as shown. The

signals D, E, and F are assumed to be low at the beginning of the timing diagram. Observe

how signal D updates (sets or resets) at positive edges of C, signal E updates (toggles) at posi-

tive edges of D, and signal F updates (sets, resets, or toggles) at negative edges of C.

FFF

set toggle set

set

reset

set

Flip-Flop Circuit Timing Diagram

EXAMPLE 6.5

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222 CHAPTER 6 Digital Circuits

6.10 APPLICATIONS OF FLIP-FLOPS

We have just seen that there are a variety of flip-flops. In the subsections below, we

illustrate a number of applications that use flip-flops as their functional units.

6.10.1 Switch Debouncing

When mechanical switches are opened or closed, there are brief current oscillations

due to mechanical bouncing or electrical arcing. This phenomenon is called switch

bounce. As illustrated in Figure 6.16 , a single closing of a switch can result in multi-

ple voltage transitions that usually occur within a few milliseconds. Video Demo 6.2

shows how switch bounce can be visualized on an oscilloscope. Video Demo 6.3

shows a very dramatic example of the arcing that occurs when a high-voltage switch

is opened or closed. In this case, a power transmission line is being shut down by a

large disconnect switch, and a very large arc forms in the process.

The sequential logic circuit shown in Figure 6.17 can provide an output that is

free from multiple transitions associated with switch bounce. As the switch breaks

contact with B, signal bounce occurs on the B line. There is a small delay as the

switch moves from contact B to A, and then signal bounce occurs on the A line as

contact is established with A. However, as a result of the feedback and logic, the

Video Demo

6.2Switch

bounce

6.3High-voltage

disconnect switch

■ CLASS DISCUSSION ITEM 6.5

JK Flip-Flop Timing Diagram

Construct a timing diagram for the negative edge-triggered JK flip-flop illustrating

its complete functionality.

■ CLASS DISCUSSION ITEM 6.6

Computer Memory

With your knowledge of flip-flops, discuss how you think computer random access

memory (RAM) works. What do you think happens to the RAM when you first turn

on a computer?

Figure 6.16 Switch bounce.

5 V

0 V

switch

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Figure 6.17 Switch debouncer circuit.

5 V

6.10 Applications of Flip-Flops 223

output signal (Q) experiences only a single transition from low to high (i.e., the

output is bounce free). The circuit functions very much like a flip-flop (see Class

Discussion Item 6.7 ).

■ CLASS DISCUSSION ITEM 6.7

Switch Debouncer Function

Track the inputs and outputs of the two NAND gates in Figure 6.17 as the switch

moves from contact B to contact A and create a timing diagram. Also, draw an

equivalent circuit for the debouncer using an RS flip-flop. Hint: Consider the gate

switch delay as was done in Figure 6.7 .

The switch shown in Figure 6.17 is called an SPDT switch, which is short for

single-pole, double-throw (see Section 9.2.1 for more information). An SPDT switch

has three leads. Section 6.12.2 shows a circuit that can be used to debounce SPST

(single-pole, single-throw) switches, which only have two leads. Class Discussion

Item 7.8 will also explore how microcontroller software can be used to debounce

switch inputs directly. This is the most efficient solution if a design happens to

include a microcontroller.

6.10.2 Data Register

Figure 6.18 shows a 4-bit data register that uses negative edge-triggered D

flip-flops to transfer data from four data lines to the outputs of four AND gates. It

does this in two distinct steps. First, the data values D

are transferred to the outputs

Q of the flip-flops on the negative edge of the load signal. Then a pulse on the read

line presents the data at the register outputs R

of the AND gates. Data registers are

used in microprocessors to hold data for arithmetic calculations. Data registers can

be cascaded to store as many bits as are required.

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Figure 6.18 4-bit data register.

load

read

Figure 6.19 4-bit binary counter.

reset

CLR

input

pulses

CLR

input

224 CHAPTER 6 Digital Circuits

6.10.3 Binary Counter and Frequency Divider

Figure 6.19 shows a 4-bit binary counter consisting of four negative edge-triggered

toggle flip-flops connected in sequence. The timing diagram is also shown for the

first 10 input pulses. The four output bits B

change according to the binary number

counting sequence, counting from 0 (B

 0000), to 1 (B

 0001),

etc., to 15 (B

 1111), and then returning back to 0. This circuit may also be

used as a frequency divider. Output B

is a divide-by-2 output because its frequency

is 1/2 the input pulse train frequency. B

, B

, and B

are divide-by 4,  8, and  16

outputs, respectively.

6.10.4 Serial and Parallel Interfaces

Figures 6.20 and 6.21 show flip-flop circuits that convert between serial and

parallel data. Serial data consists of a sequence of bits, or train of pulses, that

occurs on a single data line. Parallel data consist of a set of bits that occurs

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Figure 6.20 Serial-to-parallel converter.

reset

serial

input

)

clock

CLR

parallel output

reset

load

clock

CLR

serial

output

out

)

parallel input

CLR

Q Q Q Q

Figure 6.21 Parallel-to-serial converter.

6.10 Applications of Flip-Flops 225

simultaneously in parallel on a set of data lines. The serial-to-parallel converter

utilizes negative edge-triggered D flip-flops, and the parallel-to-serial converter

utilizes negative edge-triggered JK flipflops. In both circuits, the serial input

or output is synchronized by a clock signal. A reset line is used to clear the flip-

flops prior to loading a set of bits. The reset line is active low, meaning that,

when the line goes low, the flip-flops are cleared, causing the outputs Q to go

low (0). The load line for the parallel-to-serial converter passes the data through

the NAND gates, storing the data line values in the flip-flops using the active

low flip-flop preset. When the load line goes high and a parallel bit ( P

) is high

(1), then the respective flip-flop is preset, resulting in a high (1) output Q. The fig-

ures show 4-bit converters, but the flip-flops can be cascaded for a larger number

of bits.

■ CLASS DISCUSSION ITEM 6.8

Converting Between Serial and Parallel Data

Looking at the Figures 6.20 and 6.21 , explain in detail the function of the circuits

that convert between serial and parallel data. Also, how is the baud rate (bits per

second) for serial transmission related to the converter’s clock speed?

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Figure 6.22 TTL and CMOS input and output levels.

TTL input

TTL output

CMOS input

CMOS output

0.8 V 2.0 V

0.5 V

0 V

5 V

2.7 V

1.5 V 3.5 V

0.05 V

4.95 V

low

high

226 CHAPTER 6 Digital Circuits

6.11 TTL AND CMOS INTEGRATED

CIRCUITS

Now that we have discussed digital signals, Boolean algebra, the formulation of

digital logic expressions, and logic devices, we are prepared to present the char-

acteristics of the actual integrated circuits that perform the various digital func-

tions. There are two families of logic devices called TTL and CMOS. TTL stands

for transistor-transistor logic devices and CMOS for complementary metal-oxide

semiconductor devices. In general, any combinational or sequential logic circuit

can be constructed with either family or with a mix of the two families, but to do this

correctly, we need to understand the differences in the electronic characteristics of

each family.

In Chapter 3, we described bipolar junction transistors that are the building

blocks for TTL logic, and MOSFETs that are the building blocks for CMOS logic.

The two states of a digital device are defined by voltages occurring within speci-

fied acceptable ranges. The states and voltages for the two families are shown in

Figure 6.22 . For comparison purposes, we assume that both families are powered by

a 5 V DC supply, although CMOS, unlike TTL, can be powered with a DC supply

between 3 V and 18 V. For a TTL digital input, logic zero (0) or low ( L ) is defined

as a value less than 0.8 V, and logic one (1) or high ( H ) is defined as a value greater

■ CLASS DISCUSSION ITEM 6.9

Everyday Use of Logic Devices

Discuss the use of combinational and sequential logic functions in items you use

every day. For each, identify the purpose of the logic function and what type you

think it is (combinational or sequential).

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Figure 6.23 TTL and CMOS output circuits.

5 V

= 5 V

TTL

CMOS

out

6.11 TTL and CMOS Integrated Circuits 227

than 2.0 V. The digital output of a TTL device typically ranges between 0 and 0.5 V

for low and between 2.7 V and 5 V for high. The input voltage range 0.8 V to 2.0 V

between the logic 0 and logic 1 states is a dead zone where the input state is unde-

fined. For a CMOS digital input, logic zero (0) or low ( L ) is defined as a value less

than 1.5 V, and logic high is defined as a value greater than 3.5 V. The digital output

of a CMOS device typically ranges between 0 and 0.05 V for low and between 4.95 V

and 5 V for high. The input voltage range 1.5 V to 3.5 V is a dead zone where the

input state is undefined.

When interfacing digital devices, in addition to understanding the voltage levels,

it is also important to know the input and output current characteristics of the devices.

Important characteristics are the amount of current a device can source (produce)

when the output is high and the amount of current the device can sink (draw) when

the output voltage is low. In manufacturer data sheets for digital devices, these char-

acteristics are usually labeled as I

or “high-level output current” for the sourcing

capability and I

or “low-level output current” for the sinking capability. Example

data sheets for TTL and CMOS devices are presented later in the section.

We now examine the equivalent output circuits for TTL and CMOS devices.

Referring to Figure 6.23 , TTL logic switches between states by forward biasing one

of the two output transistors. This output circuit is called a totem pole configuration,

where two bipolar junction transistors are stacked between power and ground. When

the upper transistor is forward biased and the bottom transistor is off, the output is

high. The resistor, transistor, and diode drop the actual output voltage to a value typi-

cally about 3.4 V. When the lower transistor is forward biased and the top transistor

is off, the output is low. You can see that the TTL device sources current when there

is a high output and sinks current when the output is low. The values of the sink and

source currents depend on the TTL subfamily. When the output of a TTL device is

connected to the input of another, the TTL device dissipates power continuously

regardless of whether the output is high or low.

CMOS logic ICs employ complementary pairs of p-type and n-type

enhancement-mode MOS transistors at their outputs, hence the name complimentary

MOS (CMOS). Referring to the CMOS output circuit in Figure 6.23 , if the input

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228 CHAPTER 6 Digital Circuits

signal to this output stage is high, the p-type transistor (top) is off and the n-type

transistor (bottom) is on, so the output is pulled low. When the input is low, the

top transistor is on and the bottom transistor is off, so the output is pulled high.

When the output is high, the device sources current; and when the output is low, the

device sinks current if there is a load attached to the output. Because the MOSFET

gates are insulated, CMOS devices consume power only when switching between

states or when there is a load attached. Therefore, a major difference between CMOS

and TTL is that TTL devices require power continuously (see Class Discussion

Item 6.10 ).

CMOS is often recommended over TTL for the following reasons:

■ When an output is unloaded or connected to other CMOS devices, CMOS

requires power only when an output switches its logic state. Therefore, CMOS

is useful in battery-operated applications where power is limited.

■ The wide power supply range of CMOS (3–18 V) provides more design

flexibility and allows use of less tightly regulated power supplies.

There are some disadvantages of CMOS:

■ CMOS is sensitive to static discharge even with internal protective diodes.

Protective packaging and static discharge during handling and assembly are

necessary; otherwise, the devices are easily damaged.

■ CMOS requires negligible input current, but its output current is also small

compared to TTL. This limits the ability of CMOS to drive large TTL fan-out

or other high current devices.

■ CLASS DISCUSSION ITEM 6.10

CMOS and TTL Power Consumption

Figure 6.23 shows the output circuits for TTL and CMOS devices. Study these

circuits and convince yourself why TTL devices require power to maintain output

levels when connected to other TTL devices and CMOS devices do not require

power when connected to other CMOS devices.

6.11.1 Using Manufacturer IC Data Sheets

Manufacturers provide data books that contain data sheets for all the devices they

manufacture. The data sheets contain all the information you might need to use the

devices in your designs, including internal schematics, pin-out connections, maxi-

mum ratings, operating conditions, and electrical and switching characteristics. The

labeling system used in TTL data books is usually in the form AAxxyzz, where AA

is the manufacturer’s prefix (SN for TI and others; DM for National Semiconductor);

xx distinguishes between military (xx  54) and industrial (xx  74) quality; y dis-

tinguishes between different internal designs (no letter: standard TTL; L: low-power

dissipation; H: high-power dissipation; S: Schottky type; AS: advanced Schottky,

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6.11 TTL and CMOS Integrated Circuits 229

LS: low-power Schottky; ALS: advanced low-power Schottky); and zz is the device

number in the data book. Schottky devices have faster switching speeds and require

less power. CMOS devices are available in the 40XXB series and the 74CXX series.

The latter is pin compatible with the TTL 74XX series. There are also different vari-

eties of the 74CXX family that provide different speed and power characteristics.

They include the 74HCXX (high-speed CMOS), 74ACXX (advanced CMOS), and

74HCTXX and 74ACTXX (high-speed CMOS with TTL threshold).

Figures 6.24 through 6.26 illustrate some of the information available in a

TTL data book. The 74LS00 QUAD NAND IC is the specific example shown

here. Internet Link 6.4 points to the entire datasheet that contains a wealth of

information, much of which you will find superfluous. Similar to other gates, the

internal design is composed of transistors, resistors, and diodes, which are eas-

ily manufactured as an integrated circuit on a silicon chip. The IC is manufac-

tured as a dual in-line package (DIP) or surface mount package (SOP) with

the pin connections illustrated in Figure 6.25 . This particular DIP has four NAND

gates on a single silicon chip, hence the name QUAD NAND gate. As mentioned

previously, two important parameters in Figure 6.26 are the current sourcing and

sinking capacities. The TTL-LS NAND gate shows an output current sourcing

limit (I

) of  0.4 mA and an output current sinking limit (I

) of 8 mA. The stan-

dard convention is to use a positive number for current entering the device. TTL

devices can usually sink much more current than they can source.

Internet Lin

6.474LS00 TTL

QUAD NAND data

sheet

Figure 6.24 NAND gate internal design.

(Courtesy of Texas Instruments, Dallas, TX)

■ CLASS DISCUSSION ITEM 6.11

NAND Magic

Even though the NAND gate circuit shown in Figure 6.24 is much more compli-

cated than basic transistor circuits we’ve seen previously, convince yourself that it

results in NAND logic.

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Figure 6.25 QUAD NAND gate IC pin-out.

(Courtesy of National Semiconductor, Santa Clara, CA)

230 CHAPTER 6 Digital Circuits

Figures 6.27 and 6.28 illustrate some of the information available in a CMOS

databook. The 4011B QUAD NAND IC is the specific example shown. Internet

Link 6.5 points to the entire data sheet. A CMOS output is composed of two com-

plementary FETs, and the high output is at the supply voltage and the low output

at ground. The positive supply voltage is denoted as V

, and the low side, usually

ground, is denoted as V

. In Figure 6.28 , the CMOS NAND operating with a supply

voltage of 5 V can sink or source 1 mA.

6.11.2 Digital IC Output Configurations

Three different types of output circuits are used in TTL devices. The most common

is the totem pole configuration, where two transistors are stacked between power

and ground as shown in Figures 6.23 and 6.24 . The second type of output circuit is

known as an open-collector output. As shown in Figure 6.29 , this configuration

requires an external pull-up resistor connected to a power supply to produce the

output states. When the output transistor is saturated (ON), V

out

is low, and when it

is in cutoff (OFF), V

out

is high. Some devices that include this type of output include

the 7401, 7403, 7405, and 7406. The third type of output circuit is known as the

tristate output, where an additional input signal controls a third output state. When

enabled, the third state produces a high-output impedance that effectively discon-

nects the output from any circuit to which it is attached. This permits attaching

multiple devices to a single line where only one output would be enabled at a time

(e.g., in the bus of a computer).

Some CMOS devices, instead of having a full CMOS output stage as shown in

Figures 6.23 and 6.27 , have an open-drain output, which is analogous to the TTL

open-collector output.

Internet Lin

6.54011B CMOS

QUAD NAND data

sheet

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