Bird J. Electrical Circuit Theory and Technology
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276 Electrical Circuit Theory and Technology
Figure 17.16
Figure 17.17 Figure 17.18
change in capacitor voltage is from CE to E, the change in discharge
current is 2E/R, resulting in a change in voltage across the resistor of
2E. This circuit is called a differentiator circuit. When R is large, the
waveform is as shown in Figure 17.18(b).
17.12 Further problems
on d.c. transients
Transients in series connected C –R circuits
1 An uncharged capacitor of 0.2
µF is connected to a 100 V, d.c.
supply through a resistor of 100 k. Determine, either graphically
or by calculation the capacitor voltage 10 ms after the voltage has
been applied. [39.35 V]
2 A circuit consists of an uncharged capacitor connected in series with
a50k resistor and has a time constant of 15 ms. Determine either
graphically or by calculation (a) the capacitance of the capacitor and
(b) the voltage drop across the resistor 5 ms after connecting the
circuit to a 20 V, d.c. supply. [(a) 0.3
µF, (b) 14.33 V]
3A10
µF capacitor is charged to 120 V and then discharged through a
1.5 M resistor. Determine either graphically or by calculation the
capacitor voltage 2 s after discharging has commenced. Also find
how long it takes for the voltage to fall to 25 V.
[105.0 V, 23.53 s]
4 A capacitor is connected in series with a voltmeter of resistance
750 k and a battery. When the voltmeter reading is steady the
battery is replaced with a shorting link. If it takes 17 s for the
voltmeter reading to fall to two-thirds of its original value, deter-
mine the capacitance of the capacitor. [55.9
µF]
D.c. transients 277
5 When a 3 µF charged capacitor is connected to a resistor, the voltage
falls by 70% in 3.9 s. Determine the value of the resistor.
[1.08 M]
6A50
µF uncharged capacitor is connected in series with a 1 k
resistor and the circuit is switched to a 100 V, d.c. supply. Determine:
(a) the initial current flowing in the circuit,
(b) the time constant,
(c) the value of current when t is 50 ms and
(d) the voltage across the resistor 60 ms after closing the switch.
[(a) 0.1 A (b) 50 ms (c) 36.8 mA (d) 30.1 V]
7 An uncharged 5
µF capacitor is connected in series with a 30 k
resistor across a 110 V, d.c. supply. Determine the time constant of
the circuit and the initial charging current. Use a graphical method
to draw the current/time characteristic of the circuit and hence deter-
mine the current flowing 120 ms after connecting to the supply.
[150 ms, 3.67 mA, 1.65 mA]
8 An uncharged 80
µF capacitor is connected in series with a 1 k
resistor and is switched across a 110 V supply. Determine the time
constant of the circuit and the initial value of current flowing. Derive
graphically the current/time characteristic for the transient condition
and hence determine the value of current flowing after (a) 40 ms and
(b) 80 ms. [80 ms, 0.11 A (a) 66.7 mA (b) 40.5 mA]
Transients in series connected L–R circuits
9 A coil has an inductance of 1.2 H and a resistance of 40 and is
connected to a 200 V, d.c. supply. Draw the current/time charac-
teristic and hence determine the approximate value of the current
flowing 60 ms after connecting the coil to the supply. [4.3 A]
10 A 25 V d.c. supply is connected to a coil of inductance 1 H and resis-
tance 5 . Use a graphical method to draw the exponential growth
curve of current and hence determine the approximate value of the
current flowing 100 ms after being connected to the supply. [2 A]
11 An inductor has a resistance of 20 and an inductance of 4 H.
It is connected to a 50 V d.c. supply. By drawing the appropriate
characteristic find (a) the approximate value of current flowing after
0.1 s and (b) the time for the current to grow to 1.5 A.
[(a) 1 A (b) 0.18 s]
12 The field winding of a 200 V d.c. machine has a resistance of 20
and an inductance of 500 mH. Calculate:
(a) the time constant of the field winding,
(b) the value of current flow one time constant after being
connected to the supply, and
(c) the current flowing 50 ms after the supply has been switched
on. [(a) 25 ms (b) 6.32 A (c) 8.65 A]
18 Operational amplifiers
At the end of this chapter you should be able to:
ž recognise the main properties of an operational amplifier
ž understand op amp parameters input bias current and offset
current and voltage
ž define and calculate common-mode rejection ratio
ž appreciate slew rate
ž explain the principle of operation, draw the circuit diagram
symbol and calculate gain for the following operational
amplifiers:
inverter
non-inverter
voltage follower (or buffer)
summing
voltage comparator
integrator
differentiator
ž understand digital to analogue conversion
ž understand analogue to digital conversion
18.1 Introduction to
operational amplifiers
Operational Amplifiers (usually called ‘op amps’) were originally made
from discrete components, being designed to solve mathematical equa-
tions electronically, by performing operations such as addition and divi-
sion in analogue computers. Now produced in integrated-circuit (IC) form,
op amps have many uses, with one of the most important being as a high-
gain d.c. and a.c. voltage amplifier.
The main properties of an op amp include:
(i) a very high open-loop voltage gain A
o
of around 10
5
for d.c. and
low frequency a.c., which decreases with frequency increase
(ii) a very high input impedance, typically 10
6
Z to 10
12
Z, such that
current drawn from the device, or the circuit supplying it, is very
small and the input voltage is passed on to the op amp with little loss
(iii) a very low output impedance, around 100 Z, such that its output
voltage is transferred efficiently to any load greater than a few
kiloohms
The circuit diagram symbol for an op amp is shown in Figure 18.1. It
has one output, V
o
, and two inputs; the inverting input, V
1
, is marked–,
and the non-inverting input, V
2
, is marked C.
Operational amplifiers 279
+
V
s
(Supply +)
−
V
s
(Supply −)
Output
V
o
V
1
V
2
Inverting
Input
Non-inverting
Input
0V (on power supply)
+
−
Figure 18.1
The operation of an op amp is most convenient from a dual balanced
d.c. power supply š V
S
(i.e. CV
S
,0,V
S
); the centre point of the supply,
i.e. 0 V, is common to the input and output circuits and is taken as their
voltage reference level. The power supply connections are not usually
shown in a circuit diagram.
An op amp is basically a differential voltage amplifier, i.e. it amplifies
the difference between input voltages V
1
and V
2
. Three situations are
possible:
(i) if V
2
>V
1
, V
o
is positive
(ii) if V
2
<V
1
, V
o
is negative
(iii) if V
2
D V
1
, V
o
is zero
In general,
V
o
= A
o
.V
2
− V
1
/ or A D
V
o
V
2
V
1
1
where A
o
is the open-loop voltage gain
Problem 1. A differential amplifier has an open-loop voltage gain
of 120. The input signals are 2.45 V and 2.35 V. Calculate the
output voltage of the amplifier.
From equation (1), output voltage,
V
o
D A
o
V
2
V
1
D 1202.45 2.35
D 1200.1 D 12 V
Transfer characteristic
A typical voltage characteristic showing how the output V
o
varies with
the input V
2
V
1
is shown in Figure 18.2.
It is seen from Figure 18.2 that only within the very small input range
P0Q is the output directly proportional to the input; it is in this range
that the op amp behaves linearly and there is minimum distortion of the
amplifier output. Inputs outside the linear range cause saturation and the
output is then close to the maximum value, i.e. CV
S
or V
S
. The limited
V
o
Saturation
Saturation
V
2
>
V
1
(
V
2
−
V
1
) µ
V
V
2
<
V
1
+
V
s
−
V
s
P
Q0
Figure 18.2
280 Electrical Circuit Theory and Technology
linear behaviour is due to the very high open-loop gain A
o
, and the higher
it is the greater is the limitation.
Negative feedback
Operational amplifiers nearly always use negative feedback, obtained by
feeding back some, or all, of the output to the inverting () input (as
shown in Figure 18.5 later). The feedback produces an output voltage
that opposes the one from which it is taken. This reduces the new output
of the amplifier and the resulting closed-loop gain A is then less than the
open-loop gain A
o
. However, as a result, a wider range of voltages can
be applied to the input for amplification. As long as A
o
× A, negative
feedback gives:
(i) a constant and predictable voltage gain A, (ii) reduced distortion of
the output, and (iii) better frequency response.
10
6
10
5
10
4
10
3
10
2
10
10110
2
10
3
10
4
10
5
10
6
10
7
Frequency (Hz)
Voltage Gain
Figure 18.3
The advantages of using negative feedback outweigh the accompanying
loss of gain which is easily increased by using two or more op amp stages.
Bandwidth
The open-loop voltage gain of an op amp is not constant at all frequencies;
because of capacitive effects it falls at high frequencies. Figure 18.3 shows
the gain/bandwidth characteristic of a 741 op amp. At frequencies below
10 Hz the gain is constant, but at higher frequencies the gain falls at a
constant rate of 6 dB/octave (equivalent to a rate of 20 dB per decade)
to 0 dB.
The gain-bandwidth product for any amplifier is the linear voltage gain
multiplied by the bandwidth at that gain. The value of frequency at which
the open-loop gain has fallen to unity is called the transition frequency f
T
.
f
T
D closed-loop voltage gain ð bandwidth 2
In Figure 18.3, f
T
D 10
6
Hz or 1 MHz; a gain of 20 dB (i.e. 20log
10
10)
gives a 100 kHz bandwidth, whilst a gain of 80 dB (i.e. 20 log
10
10
4
)
restricts the bandwidth to 100 Hz.
18.2 Some op amp
parameters
Input bias current
The input bias current, I
B
, is the average of the currents into the two input
terminals with the output at zero volts, which is typically around 80 nA
(i.e. 80 ð 10
9
A) for a 741 op amp. The input bias current causes a volt
drop across the equivalent source impedance seen by the op amp input.
Input offset current
The input offset current, I
os
, of an op amp is the difference between the
two input currents with the output at zero volts. In a 741 op amp, I
os
is
typically 20 nA.
Operational amplifiers 281
Input offset voltage
In the ideal op amp, with both inputs at zero there should be zero output.
Due to imbalances within the amplifier this is not always the case and
a small output voltage results. The effect can be nullified by applying
a small offset voltage, V
os
, to the amplifier. In a 741 op amp, V
os
is
typically 1 mV.
Common-mode rejection ratio
The output voltage of an op amp is proportional to the difference between
the voltages applied to its two input terminals. Ideally, when the two
voltages are equal, the output voltages should be zero. A signal applied
to both input terminals is called a common-mode signal and it is usually
an unwanted noise voltage. The ability of an op amp to suppress common-
mode signals is expressed in terms of its common-mode rejection ratio
(CMRR), which is defined by:
CMRR
= 20 log
10
differential voltage gain
common mode gain
dB 3
In a 741 op amp, the CMRR is typically 90 dB.
The common-mode gain, A
com
, is defined as:
A
com
=
V
o
V
com
4
where V
com
is the common input signal
Problem 2. Determine the common-mode gain of an op amp that
has a differential voltage gain of 150 ð 10
3
and a CMRR of 90 dB.
From equation (3),
CMRR D 20log
10
differential voltage gain
common mode gain
dB
Hence 90 D 20log
10
150 ð 10
3
common mode gain
from which 4.5 D log
10
150 ð 10
3
common mode gain
and 10
4.5
D
150 ð 10
3
common mode gain
Hence, common-mode gain D
150 ð 10
3
10
4.5
= 4.74
282 Electrical Circuit Theory and Technology
Problem 3. A differential amplifier has an open-loop voltage gain
of 120 and a common input signal of 3.0 V to both terminals. An
output signal of 24 mV results. Calculate the common-mode gain
and the CMRR.
From equation (4), the common-mode gain,
A
com
D
V
o
V
com
D
24 ð 10
3
3.0
D 8 ð 10
3
D 0.008
From equation (3), the
CMRR D 20 log
10
differential voltage gain
common mode gain
dB
D 20log
10
120
0.008
D 20log
10
15000 D 83.52dB
Slew rate
The slew rate of an op amp is the maximum rate of change of output
voltage following a step input voltage. Figure 18.4 shows the effects of
slewing; it causes the output voltage to change at a slower rate that the
input, such that the output waveform is a distortion of the input waveform.
0.5 V/
µs is a typical value for the slew rate.
Ideal output
Actual
output
Time
0
+
V
s
−
V
s
Figure 18.4
18.3 Op amp inverting
amplifier
The basic circuit for an inverting amplifier is shown in Figure 18.5 where
the input voltage V
i
(a.c. or d.c.) to be amplified is applied via resistor
R
i
to the inverting () terminal; the output voltage V
o
is therefore in
anti-phase with the input. The non-inverting (C) terminal is held at 0 V.
Negative feedback is provided by the feedback resistor, R
f
, feeding back
a certain fraction of the output voltage to the inverting terminal.
Amplifier gain
In an ideal op amp two assumptions are made, these being that:
(i) each input draws zero current from the signal source, i.e. their input
impedance’s are infinite, and
(ii) the inputs are both at the same potential if the op amp is not satu-
rated, i.e. V
A
D V
B
in Figure 18.5.
In Figure 18.5, V
B
D 0, hence V
A
D 0 and point X is called a virtual
earth.
Thus, I
1
D
V
i
0
R
i
and I
2
D
0 V
o
R
f
V
i
I
1
I
2
R
i
R
f
X
+
−
V
A
V
B
V
o
0V
Figure 18.5
Operational amplifiers 283
However, I
1
D I
2
from assumption (i) above.
Hence
V
i
R
i
D
V
o
R
f
,
the negative sign showing that V
o
is negative when V
i
is positive, and
vice versa.
The closed-loop gain A is given by:
A =
V
o
V
i
=
−
R
f
R
i
5
This shows that the gain of the amplifier depends only on the two resistors,
which can be made with precise values, and not on the characteristics of
the op amp, which may vary from sample to sample.
For example, if R
i
D 10 k and R
f
D 100 k, then the closed-loop gain,
A D
R
f
R
i
D
100 ð10
3
10 ð 10
3
= −10
Thus an input of 100 mV will cause an output change of 1 V.
Input impedance
Since point X is a virtual earth (i.e. at 0 V), R
i
may be considered to be
connected between the inverting () input terminal and 0 V. The input
impedance of the circuit is therefore R
i
in parallel with the much greater
input impedance of the op amp, i.e. effectively R
i
. The circuit input impe-
dance can thus be controlled by simply changing the value of R
i
.
Problem 4. In the inverting amplifier of Figure 18.5, R
i
D 1k
and R
f
D 2k. Determine the output voltage when the input
voltage is: (a) C0.4 V (b) 1.2 V
From equation (5), V
o
D
R
f
R
i
V
i
(a) When V
i
DC0.4V,V
o
D
2000
1000
C0.4 D −0.8V
(b) When V
i
D1.2 V, V
o
D
2000
1000
1.2 D Y2.4V
Problem 5. The op amp shown in Figure 18.6 has an input bias
current of 100 nA at 20
°
C. Calculate (a) the voltage gain, and
(b) the output offset voltage due to the input bias current. (c) How
can the effect of input bias current be minimised?
R
1
= 10 kΩ
R
2
= 1 MΩ
V
i
V
o
+
−
Figure 18.6
284 Electrical Circuit Theory and Technology
Comparing Figure 18.6 with Figure 18.5, gives R
i
D 10 k and R
f
D
1M
(a) From equation (5), voltage gain,
A D
R
f
R
i
D
1 ð 10
6
10 ð 10
3
D −100
(b) The input bias current, I
B
, causes a volt drop across the equivalent
source impedance seen by the op amp input, in this case, R
i
and R
f
in parallel. Hence, the offset voltage, V
os
, at the input due to the
100 nA input bias current, I
B
, is given by:
V
os
D I
B
R
i
R
f
R
i
C R
f
D 100 ð 10
9
10 ð 10
3
ð 1 ð 10
6
10 ð 10
3
C 1 ð 10
6
D 10
7
9.9 ð 10
3
D 9.9 ð 10
4
D 0.99 mV
(c) The effect of input bias current can be minimised by ensuring that
both inputs ‘see’ the same driving resistance. This means that a
resistance of value of 9.9 kZ (from part (b)) should be placed
between the non-inverting (+) terminal and earth in Figure 18.6.
Problem 6. Design an inverting amplifier to have a voltage gain
of 40 dB, a closed-loop bandwidth of 5 kHz and an input resistance
of 10 k
The voltage gain of an op amp, in decibels, is given by:
gain in decibels D 20log
10
(voltage gain) from chapter 10
Hence 40 D 20log
10
A
from which, 2 D log
10
A
and A D 10
2
D 100
With reference to Figure 18.5, and from equation (5),
A D
R
f
R
i
i.e. 100 D
R
f
10 ð 10
3
Hence R
f
D 100 ð 10 ð 10
3
D 1MZ
From equation (2), Section 18.1,
frequency D gain ðbandwidth D 100 ð 5 ð 10
3
D 0.5MHz or 500 kHz
Operational amplifiers 285
Further problems on the introduction to operational amplifiers may be
found in Section 18.12, problems 1 to 6, page 294.
18.4 Op amp
non-inverting amplifier
The basic circuit for a non-inverting amplifier is shown in Figure 18.7
where the input voltage V
i
(a.c. or d.c.) is applied to the non-inverting
(C) terminal of the op amp. This produces an output V
o
that is in phase
with the input. Negative feedback is obtained by feeding back to the
inverting () terminal, the fraction of V
o
developed across R
i
in the
voltage divider formed by R
f
and R
i
across V
o
+
−
V
i
R
f
R
i
V
o
0V
Figure 18.7
Amplifier gain
In Figure 18.7, let the feedback factor,
ˇ D
R
i
R
i
C R
f
It may be shown that for an amplifier with open-loop gain A
o
, the closed-
loop voltage gain A is given by:
A D
A
o
1 C ˇA
o
For a typical op amp, A
o
D 10
5
, thus ˇA
o
is large compared with 1, and
the above expression approximates to:
A D
A
o
ˇA
o
D
1
b
(6)
Hence
A =
V
o
V
i
=
R
i
Y R
f
R
i
= 1 Y
R
f
R
i
(7)
For example, if R
i
D 10 k and R
f
D 100 k,
then A D 1 C
100 ð 10
3
10 ð 10
3
D 1 C 10 D 11
Again, the gain depends only on the values of R
i
and R
f
and is indepen-
dent of the open-loop gain A
o
Input impedance
Since there is no virtual earth at the non-inverting (C) terminal, the input
impedance is much higher (typically 50 MZ) than that of the inverting
amplifier. Also, it is unaffected if the gain is altered by changing R
f
and/or R
i
. This non-inverting amplifier circuit gives good matching when
the input is supplied by a high impedance source.