Baca A.G., Ashby C.I.H. Fabrication of GaAs Devices

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Semiconductor properties

to make the chips ﬁt properly in their package and to make

them easier to scribe and break. Substrates for low-frequency

or low-power applications are often lapped to a thickness of

250 μm. High-frequency or high-power applications require thin-

ner wafers. Power ampliﬁers must have a means of dissipating

the heat generated without causing too great an increase in the

junction temperature. The best means of accomplishing this goal

is to thin the wafer to make a low thermal resistance path to a

heat sink in the package. For thermal reasons, thinner is better,

but somewhere in the range of 50–100 μm is the practical lower

limit for subsequent handling of the dice. Electrical reasons for

thinning wafers are related to the design of monolithic microwave

integrated circuits (MMIC). The physical size of the transmission

lines is proportional to the thickness of the wafer. Circuit size can

be minimised by thinning wafers. Also, via holes are impractical

to etch in overly thick wafers.

Once lapping is completed, the wafer can be polished. The pur-

pose of this step is to remove mechanical damage and to restore

an optical ﬁnish for subsequent lithography steps. The polish can

use a combination of a very ﬁne grit impregnated in a polishing

pad and an etchant. This ﬁnal step is relatively brief compared to

the rest of the wafer thinning process.

Next the wafer is cleaned and further processed. For high-

frequency devices and MMICs, perhaps 10 GHz and above, a

low-inductance method of grounding a transistor is needed. Wire

bonds from a frontside groundpad to a backside ground plane have

signiﬁcant and variable inductance that is problematic for design-

ing microwave circuits. For this reason, via holes to the backside

of the wafer are made to provide a direct, low-inductance ground.

The lapped wafer, still mounted to a carrier substrate, is patterned

with the via hole mask using photolithography. The GaAs is then

etched through the substrate until the metal pad on the frontside

of the wafer is reached. At this point, the resist is stripped from

the backside of the wafer and the wafer is prepared for backside

metallisation.

Backside metallisation is necessary to make electrical contact to

the frontside of the wafer through the via holes. A good backside

metal also allows the ﬁnished chips to be attached to a package

or carrier with a metal-based die-attach process. An epoxy die

attach may be used for low-power and low-cost processes. It is

necessary to uniformly coat the backside of the wafer, the sides of

the via holes and the bottom with a low-resistance metal in order

to ensure good electrical contact to the frontside of the wafer,

and sputter deposition is usually a good way to accomplish this

goal. After deposition, the metal is usually thickened by electro-

plating to increase the conductivity of the via hole. In order to

Semiconductor properties

facilitate die separation, the wafer is often patterned in order to

avoid electroplating in the streets between chips (die).

Once the backside metallisation is complete, the wafer is ready

for die separation. Three choices are available for die separation:

dicing, sawing and etching. Etching is not often used for die sep-

aration and won’t be discussed further. Dicing is accomplished by

dragging a diamond stylus along the surface of the wafer parallel

to one of the cleavage planes. The scratches created by this pro-

cess initiate fractures along the scribe lines. The scribing process

requires dismounting the wafer to ﬁnish the cleaving process. The

sawing process utilises high-speed circular saws to cut through the

GaAs. The same host substrate used in backside processing can

be used for sawing. If this choice is made, the chips are separated

from the host substrate using solvents to dissolve the adhesive used

in the mounting process. This process leaves a pile of chips that

need to be sorted.

Instead of sawing with the wafer still mounted to the host sub-

strate, one can remove it ﬁrst, as with the dicing process. A vacuum

wand the size and shape of the wafer holds the wafer from the

backside as the host substrate is heated. Then the wafer is pulled

sideways to slide the wafer off. After cleaning off the wafer, it

is mounted backside down (using another vacuum wand trans-

fer) on sticky, stretchable tape held taut in a frame (for handling).

The wafer is then diced or sawed. After scribing, the chips are

separated by moving rollers (specially sized metal cylinders, usu-

ally) over the wafer and the gentle pressure breaks the dice. This

whole process is automated in modern scribe and break machines.

Once either sawed or diced wafers are separated on the tape, the

tape can be stretched. The stretched tape allows individual die to be

removed from the tape. The tape stickiness is sufﬁcient for holding

down the wafer, but will allow individual die to be removed with

a small force such as the pull of a vacuum wand.

Once the chips are separated, they are ready for packaging. The

good die were preferably identiﬁed at wafer level test and now

can be picked from the stretched tape and placed in a package.

In high-volume factories, pick-and-place machines are available

to do this job quickly and accurately. Otherwise, tweezers and

hand labour are appropriate. The chips are bonded to the pack-

age with epoxy, solder or metal-based die attach. The latter two

are more appropriate for high-power devices because a metal

bond has better thermal conductivity. The solder is available in

“preforms”, appropriately sized for the die being packaged. The

package is then heated to complete the eutectic or solder die attach

process.

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2.7.2 Reliability

Finished devices must test well and meet all speciﬁcations of the

end application. They must then meet the customer requirements

for ambient operating conditions over a speciﬁed lifetime. It is the

purpose of reliability analysis to ensure that the devices meet these

requirements and to uncover and study degradation mechanisms.

Although reliability analysis is a ﬁeld in itself, reliability studies

are not done in isolation because it is not enough to evaluate device

longevity and degradation mechanisms. One must also be able to

uncover the causes for unacceptable degradation and have the abil-

ity to control or eliminate them. Process and material engineers

must be intimately involved in the reliability process to engineer

robust processes.

One difﬁcult aspect of reliability analysis is the long times

required to evaluate a batch of devices. Customers will typically

specify operating lifetimes at a maximum operating temperature

and bias conditions, often for ten years or more with low failure

rates. Manufacturers don’t have the luxury of waiting that long

to test the parts so they look for ways to accelerate the testing.

Acceleration is usually done by using some form of extra stress-

ing of the device, typically using elevated temperature or bias

stress. It is often found that device lifetime follows the Arrhenius

equation:

F = F

exp(E

/kT) (2.22)

where F is the median time to failure, F

is a constant, E

is the

activation energy, k is the Boltzman constant and T is the tem-

perature. The Arrhenius equation applies if a single degradation

mechanism is responsible and a single value of E

represents the

activation energy of the degradation process. When EQN (2.22)

applies, the failure rate will be linear with the logarithm of T and

data from several temperatures can be taken to extractthe activation

energy. Once the activation energy is known, the median time to

failure at the maximum operating temperature can be extrapolated.

Typically three temperatures are chosen to do the study. One

chooses a set of samples for each temperature, often with as few

as 5–9 samples for initial studies, and conducts the study until

half of the samples have failed. For larger populations of samples,

a log normal plot of percentage failed versus time is plotted. If

the population follows a straight line (the population is said to

follow a log normal distribution), one can have greater conﬁdence

extrapolating the median failure time without proceeding until half

of the devices fail, thus saving precious test time, but at the expense

of using more devices and tying up more equipment.

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The art and skill of reliability analysis is in dealing with the

non-idealities of the real world. Even if the assumption of a single

activation energy is valid, one still faces the challenge of ﬁnding

the right choice of temperatures to use. If one is too conservative

with low temperatures, the test may take a very long time. Being

too aggressive has its pitfallsas well, since too high a choice of tem-

perature may accelerate a failure mechanism that does not apply at

operating temperatures. In order to gain insight into these difﬁcult

tradeoffs, a reliability engineer will often resort to a step stress

study prior to undertaking a full reliability study. The stressing

condition will be stepped at regular (but short) time intervals for

a population of devices and the failures and degradations at each

time intervalare noted. Thecumulative failure rate is plotted versus

time with regular steps in the stress condition. One may also char-

acterise devices after each stress condition to analyse samples for

material degradation, electrical degradation or catastrophic failure.

From such analysis, one often gains insight for designing better

studies.

Although we have illustrated the principles of reliability using

temperature as the stressor, electric ﬁeld or current density can

be equally important stressors for FETs and HBTs (Chapters 8

and 9). In general, one can keep the junction temperature constant

by careful manipulation of the ambient temperature and the device

self-heating.

The process engineer uses the results of reliability studies to

engineer better devices and to get a better idea of which epi-

taxy, which ohmic contact (Chapter 6), which Schottky contact

(Chapter 7) or which process of interest is most robust. Chapters 8

and 9 give some examples of the main reliability issues for

GaAs-based FETs and HBTs.

Eliminating changes in device operation during long-term oper-

ation is the goal for designing high-reliability devices. Sometimes,

if this goal is not totally achieved, another procedure called burn-in

can be acceptable. For burn-in, all devices are electrically biased

for a short period (up to several hours) of time. The purpose of this

procedure is twofold: to allow weak devices to fail quickly and to

stabilise devices that drift upon initial operation.

We’ll conclude this section with a warning that reliability data

is a powerful marketing tool and can be subject to manipulation.

Device manufacturers and their customers, original equipment

manufacturers (OEMs), engage in ﬁerce negotiations over reli-

ability speciﬁcations. The OEM wants to have very few product

returns (perhaps speciﬁed in returns per thousand) and some-

times places unrealistic demands on its suppliers. The supplier

feels this intense pressure to not only produce great reliabil-

ity, but to do so early in a technology cycle (read new GaAs

Semiconductor properties

device) with never enough time to do careful studies and with

intense competition with other potential suppliers. Further, the

supplier may be in a better position than the OEM to under-

stand the technology tradeoffs and may conclude (or gamble)

that many causes of early product returns will be unrelated to

the GaAs devices and will agree to impossibly aggressive reli-

ability speciﬁcations for GaAs devices. Often the result is an early

unrealistic reliability study presented at a conference that gen-

erates interest and excitement. The study will be likely to have

been accelerated with too high temperatures that give an unreal-

istically high activation energy and a wonderful extrapolation to

lower temperatures showing million hour or better “reliability”.

The GaAs process engineer should look with a critical eye at

all assumptions or lack of details concerning them and learn to

understand the difference between reliability hype and careful

studies.

2.7.3 Failure analysis

When devices have failed, it is often of interest to determine the

failure mechanism, particularly if one has gained some special

insight into the device through prior specialised testing, through

reliability testing or through a ﬁeld return of a product. By identi-

fying failures, one can highlight aspects of the process that can be

modiﬁed for improvement. Many failure analysis techniques were

described in Section 2.5. Some of the more useful ones include

FIB, SEM, TEM and SIMS. Many specialised techniques have

also been developed for failure analysis.

2.8 CONCLUSION

Background material for GaAs processing was presented in this

chapter for easy reference and to give an overview of GaAs

technology. The material presented includes semiconductor phys-

ics, GaAs material growth technology, methods of characterisation

and an overview of the entire product realisation process. The

explanations and descriptions were simpliﬁed and condensed to

ﬁt in one chapter. They are not a substitute for in depth study of

any particular subject area, but rather intended as a concise ref-

erence for material in later chapters or a starting point for further

study. The authors also believe that a reader should not have to

interrupt reading material to consult detailed reference books on

speciﬁc subject areas when concise summaries are sufﬁcient for

the purpose at hand.

Semiconductor properties

REFERENCES

[1] S.M. Sze [Physics of Semiconductor Devices (John Wiley and Sons,

New York, 1981)]

[2] S.L. Chuang [Physics of Optoelectronic Devices (John Wiley and Sons,

New York, 1995)]

[3] M. Shur [Physics of Semiconductor Devices (Prentice Hall, Englewood

Cliffs, NJ, USA, 1990)]

[4] C.M. Wolfe, N. Holonyak Jr., G.W. Stillman [Physical Properties of

Semiconductors (Prentice Hall, Englewood Cliffs, NJ, USA, 1989)]

[5] M.R. Brozel, G.E. Stillman (Eds) [Properties of GaAs, Third Edition (IEE,

London, UK, 1996)]

[6] N.W. Ashcroft, N.D. Mermin [Solid State Physics (Holt, Rinehart,

Winston, New York, 1976)]

[7] P. Philips [Advanced Solid State Physics (Westview Press,

Cambridge, MA, 2003)]

[8] P. Rudolph, M. Jurisch [J. Cryst. Growth (Netherlands) vol.198/199

(1999) p.325]

[9] J.Y. Tsao [Materials Fundamentals of Molecular Beam Epitaxy

(Academic Press, Boston, 1993)]

[10] W.G. Breiland, K.P. Killeen [J. Appl. Phys. (USA) vol.78 (1995) p.6726]

[11] D.R. Brundle, C.A. Evans Jr., S. Wilson (Eds) [Encyclopedia of Materials

Characterization (Butterworth-Heinemann, Boston, MA, USA, 1992)]

[12] D.K. Schroder [Semiconductor Material and Device Characterization,

Second Edition (John Wiley and Sons, New York, 1998)]

[13] R. Williams [Modern GaAs Processing Methods, Second Edition (Artech

House, Boston, 1990)]

[14] S.J. Pearton, C.R. Abernathy, F. Ren [Topics in Growth and Device

Processing of III-V Semiconductors (World Scientiﬁc, Singapore, 1996)]

[15] S. Mahajan, K.S. Sree Harsa [Principles of Growth and Processing of

Semiconductors (WCB McGraw-Hill, Boston, MA, USA, 1999)]

[16] M. Madau [Fundamentals of Microfabrication (CRC Press, Boca Raton,

FL, USA, 1997)]

[17] S.K. Ghandi [VLSI Fabrication Principles: Silicon and Gallium Arsenide,

Second Edition (John Wiley and Sons, New York, 1994)]

Chapter 3

Cleaning and passivation of GaAs and

related alloys

Chapter scope p.69

Cleaning and native oxide

removal p.69

Removal of organic and metal ion

contaminants p.69

Removal of native oxide p.71

Regrowth of native oxide p.72

Passivation of GaAs p.74

Electronic properties of the GaAs

surface p.75

Chalcogenide passivation: S and

Se p.91

Passivation for improved

semiconductor regrowth p.101

Passivation for improved contact

metallisation p.102

Special oxide passivations p.106

Dielectric passivations: PECVD and

ECR SiN

and SiO

p.109

Conclusion p.114

References p.114

3.1 CHAPTER SCOPE

The surface quality of GaAs is very important in the reproducible

fabrication of devices. There are two rather distinct aspects of sur-

face quality: cleanliness and electronic passivation. Both aspects

are the topics of this chapter. We begin with a practical discussion

of surface treatments aimed at the removal of organic contamin-

ants and native oxides from the semiconductor surfaces. We will

then proceed to a review of the electronic properties of the gallium

arsenide surface, especially those of its native oxide, and discuss

approaches to improve those properties, i.e. to passivate the surface

to improve device performance.

3.2 CLEANING AND NATIVE OXIDE REMOVAL

The surface cleaning of GaAs and other semiconductors involves

two different aspects. The ﬁrst is the removal of contaminants,

such as organic compounds and metal ions. The second is the

removal of the native oxide to expose the bare semiconductor for

subsequent processing such as metal contact deposition.

3.2.1 Removal of organic and metal ion contaminants

The surface of a semiconductor wafer can pick up organic con-

taminants in much more subtle ways than by being handled

incautiously so as to allow it to come into direct contact with some-

thing greasy (including ﬁngers). There are always some organic

vapours in the air of a clean room, and a wafer that has been

exposed to them for even a moderate amount of time can become

contaminated.

An organic solvent cleaning protocol can be used to remove

serious organic contamination. Some protocols are especially

suitable for preparing a wafer surface for growth. One such

protocol for gross degreasing consists of the following sequences

Cleaning and passivation of GaAs and related alloys

of treatments with different organic solvents: 1) boil for 10 min in

1,1,1-trichloroethane (TCE), 2) boil for 10 min in acetone, 3) soak

for 10 min in methanol and 4) soak for 10 min in isopropanol (IPA

or isopropyl alcohol). This works well for GaAs and InP. For

antimonides such as GaSb, which form chemically resistant oxides

that do not readily desorb at high temperature, a 10 s oxide removal

step with 1 : 1 HCl/H

O precedes the organic solvent cleans. When

the surface is not heavily contaminated by organics, a 10 min boil

in acetone, a 5 min boil in methanol and a DI water rinse can be

sufﬁcient. Note that heating organic solvents can be a ﬁre hazard.

This is especially true with acetone, which has a very low ﬂash-

point, so extreme caution should be employed and any potential

sources of electrical sparks should be kept well away. Boiling may

well not be necessary to achieve sufﬁcient cleanliness; avoid the

hazard whenever possible. Sonication using ultrasound can often

be used as an alternative to boiling to enhance cleaning efﬁciency.

Degreasing

1) Trichloroethane (TCE)

2) Acetone

3) Methanol

4a) Isopropanol (IPA)

4b) DI Water

Thermal deoxidation

1) Degrease surface.

2) Heat under column V source gas

with no oxygen present.

For optoelectronic devices, a semiconductor surface may have

been patterned by etching prior to a second insertion into an MBE

or MOCVD growth chamber for regrowth of additional semicon-

ductor layers. It is especially important in these cases to obtain

a clean and oxide-free surface before beginning regrowth or an

unacceptable number of defects may exist in the ﬁnal wafer. While

the preceding process removes organic contaminants, the surface

layer is still a native oxide rather than the simple binary or tern-

ary semiconductor that one wishes to use as the growth template.

If oxide is present on the surface as growth is initiated, a highly

defected interface between the former and latter grown materials

will be present. In general, this oxide is removed by heating in

the growth chamber in the presence of a column V source gas. The

speciﬁc heating protocol will depend on the growth technique, the

semiconductor material, and the composition of material that is

to be regrown on the surface; good deoxidation recipes are avail-

able in the literature for a variety of materials. An example of

an oxide removal process for MOCVD growth on GaAs involves

heating under AsH

ﬂow at 750

◦

C for 15 min before initiating

growth. Similarly, InP can be prepared for growth by heating at

650

◦

C for 15 min under a ﬂow of the P-source gas. Heating over

600

◦

C in the absence of a column V source gas will lead to excess

elemental Ga on the surface. Heating under the column V source

gas is also effective for MBE growth.

If oxide formation on the surface is not an issue or if the oxide is

to be removed before later processing, atomic oxygen can be used

to remove traces of residual organics. Ozone is a good source of

atomic oxygen that produces no atomic displacement damage at

the semiconductor surface. Commercial ozone cleaning tools are

readily available. A very-low-energy oxygen plasma can also be

Cleaning and passivation of GaAs and related alloys

used. This plasma cleaning approach is discussed in greater detail

in Section 5.5. The tool employed for this approach is often referred

to as an “asher” or barrel etcher. The sample is immersed in the

plasma so that the energy of the bombarding ions is less than 10 eV,

well below the atomic displacement threshold of approximately

40 eV for compound semiconductors.

Removal of Metal Ions

1) NH

OH rinse.

2) DI water rinse.

For removal of metal ion contaminants, rinsing with chemicals

that can form complexes with a wide variety of metal ions can

be quite effective. Ammonium hydroxide solutions are an excel-

lent choice for this. NH

OH is formed by dissolving NH

in water:

O ↔ NH

OH. The ammonium ion is in equilibrium with

ammonia (NH

) in solution and ammonia is known to form soluble

metal complexes, M(NH

)

, with many transition metals. This

is highly desirable since transition metals can degrade electronic

properties. Two additional advantages of NH

OH solutions are

their ability to remove the native oxide of GaAs and their sapon-

iﬁcation capability. Saponiﬁcation is the process of hydrolysing

a fat (a fatty acid ester) with OH

−

to form glycerol and a fatty

acid salt (soap), both of which are highly soluble. This ability to

solubilise oils and greases is shared by other hydroxides, such as

NaOH and KOH, but these two bases do not form metal ion com-

plexes, and Na-containing solutions are themselves a source of

metal ion contamination. It is worth noting that “pure” de-ionised

(DI) water (15 MΩ or higher resistance) will also readily dissolve

metal ion contaminants.

3.2.2 Removal of native oxide

While an NH

OH/H

O solution will assist in the removal of

organic and metallic impurities, its primary role as a surface treat-

ment is in the removal of native oxide from the GaAs surface.

Useful dilutions range from 1 : 10 to 1 : 20 NH

OH/H

O. Irriga-

tion (sweeping the surface with a stream from a squeeze bottle)

for 30 s generally works well. Dilute acidic solutions, such as

1 : 1 HCl/H

O or dilute H

or H

, can also be used. An

understanding of the process of native oxide formation and the dif-

ferences in the surface composition resulting from using different

oxide removers can guide the selection of the most appropriate

solution.

All the III–V semiconductors are readily oxidised by atmo-

spheric oxygen, so the surface of GaAs and other compound

semiconductors that have been exposed to air will be covered

by a thin layer of native oxide. This is typically of the order of

1–2 nm after long-term air exposure. Immersion in either acidic

or basic dilute solutions will dissolve the native oxide. If no oxid-

iser, such as H

, is present, there will be negligible dissolution