Baca A.G., Ashby C.I.H. Fabrication of GaAs Devices

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Semiconductor properties

2.2.3 Carrier transport and continuity equations

Under normal operating conditions there are two types of car-

rier transport in semiconductors: drift, which is the response of

a charged particle to an electric ﬁeld, and diffusion, which is a

response to a concentration gradient. In a semiconductor, a charged

particle in an electric ﬁeld, E, experiencesa force which accelerates

the particle, but it will not accelerate indeﬁnitely because collisions

with the lattice can redirect its energy and velocity. At any given

electric ﬁeld, an average velocity will result, which represents the

net average of the response to the electric ﬁeld, collisions with the

lattice, and random thermal motion. The electron drift mobility is

a parameter that relates the electron or hole velocity to the applied

electric ﬁeld,

= μ

E (2.8)

where μ

is the drift mobility, E is the electric ﬁeld and v

is the

drift velocity. From the drift velocity, a current density is given by

= qnμ

E (2.9)

where J

is the electron current density, and the other parameters

were previously deﬁned. An equivalent expression for hole cur-

rent can be used. EQNS (2.8) and (2.9) imply that velocity and

current density can increase without limit as E is increased. On the

contrary, as the particles get more energetic, the effects of scat-

tering and electric ﬁeld acceleration balance and offset each other

and velocity saturation occurs. The electrons can also scatter more

easily into higher bands. An electron, for example, can scatter

from the Γ band of FIGURE 2.3 to the L band and its transport

degrades due to the higher effective mass in the L band. Thus, at

higher electric ﬁelds, the electron velocity is an average of those in

the Γ and L bands and actually decreases at higher electric ﬁelds.

In general, the electron velocity for GaAs looks something like

that of FIGURE 2.7. At low electric ﬁeld the electron velocity is

linear with electric ﬁeld and is well described by its drift mobil-

ity. At intermediate electric ﬁeld, the electron velocity peaks and

overshoots its high ﬁeld value. The saturated electron velocity is

given by the high-ﬁeld value. The important transport properties

depend on the speciﬁcs of the device design, which determine

electric ﬁelds for the operating conditions of that design (more in

Sections 8.2 and 9.2), and in particular, whether low-ﬁeld mobility,

the saturated velocity or the velocity overshoot is more important.

0.5

1.5

5101520

electric field (1000 V/cm)

025

2.5

electron velocity (10

cm/s)

FIGURE 2.7 The electron

velocity versus electric ﬁeld for

GaAs.

A second type of carrier transport is diffusion, or response to

a concentration gradient, which may occur in a semiconductor

device as a result of how its ﬁxed carriers are distributed. In one

Semiconductor properties

dimension, for simplicity, this current is given by

= qD

(dn/dx) (2.10)

where D

is the diffusion coefﬁcient for electrons and the other

parameters are as before. A similar equation describes the diffusion

current for holes. In a pn junction, for example, this type of current

will continue until an electric ﬁeld is set up to oppose any further

current ﬂow. The carrier transport equations for both electrons and

holes are given by:

= qnμ

E + qD

(dn/dx)

= qpμ

E + qD

(dp/dx)

(2.11)

Continuity equations are used to solve for transport in semicon-

ductor devices. In many cases of commonly studied devices, these

equations are solved in semiconductor device books, as examples,

or in seminal research papers. Most readers will have no need

to solve these equations, but should be aware of their use, not

only in advanced textbooks, but also in commercially available

device simulation packages. These equations are solved simultan-

eously with any other equations, such as the Poisson equation, that

describe the physics of the device. In one dimension, the continuity

equations are

(dn/dt) = G

− U

+ q

−1

(d (J

)/dx)

(dp/dt) = G

− U

+ q

−1

(d (J

)/dx)

(2.12)

where G

) is the generation rate for electrons (holes),

) is the recombination rate for electrons (holes), and the

other symbols are as previously deﬁned.

2.3 BULK CRYSTAL GROWTH

Semiconductor crystals, including GaAs, are grown from a liquid

“melt” with a small single crystal “seed” used as the starting mater-

ial. An ingot or boule of material is grown from the seed as it

is pulled from the melt and the interface between the melt and

the crystal forms a growing surface. The melt is conﬁned in an

enclosed area constrained in ways deﬁned by the speciﬁc method

of growth and is usually grown as a boule that is one to several

times longer than the diameter of the wafer desired. After growth,

the boule is removed from the crucible (container), ground to the

Semiconductor properties

desired diameter, and sliced into wafers which are lapped and pol-

ished. Electronic devices require high-resistivity semi-insulating

GaAs (>10

-cm) in contrast to many photonic devices, which

generally require doped substrates. Ideally, GaAs wafers are

extremely pure and free of defects. In practice, GaAs wafers

do have reasonably high purity (7–8 orders of magnitude lower

impurity concentration than the effective GaAs “concentration”).

However, temperature non-uniformities that exist both at the

growth front and during the cooling process cause stresses in

the GaAs crystal, which lead to the formation of dislocations.

Most of the art in GaAs growth is aimed at producing econom-

ical, high-yield substrates with both radial and axial uniformity

while minimising dislocations and achieving uniform high res-

istivity. Other parameters of interest for the sliced wafer include

ﬂatness and surface preparation for epitaxial growth (Section 2.4).

As if these were not challenging enough requirements, manufac-

turing technology progresses relentlessly towards larger diameter

substrates, which bring additional challenges for temperature

uniformities and other manufacturing issues in boule growth.

Section 2.3.1 gives an overview of the major types of crys-

tal growth in use today. A great amount of ﬂexibility exists

in the choice of technology available to meet the requirements of

the device engineer. Section 2.3.1 will present a discussion on the

tradeoffs in substrate properties, substrate technology and device

requirements.

The basics of the two main growth methods are presented in the

rest of this section. As the details of each method are introduced,

their inﬂuence on substrate quality is discussed.

2.3.1 Methods of crystal growth

The main methods of crystal growth in use nowadays fall into two

categories: Czochralski methods and Bridgman methods. Histori-

cally, liquid encapsulated Czochralski (LEC, FIGURE 2.8(a)) and

horizontal Bridgman were commercially available earlier than

today’s vertical Bridgman methods and produced low-cost wafers.

The early horizontal Bridgman method did not compete well with

LEC because it produced D-shaped ingots, which required oblique

slicing and its associated material waste to obtain round wafers.

In the Czochralski method, a seed crystal is placed over a GaAs

melt contained in a heated crucible that is held at a temperat-

ure close to the liquid-solid phase transition. The seed crystal is

moved upwards under continuous rotation. The Bridgman method

involves the directed solidiﬁcation of a melt starting from the

seed. The solidiﬁcation direction can be vertical or horizontal.

The movement of the crystal interface with the liquid can be

Semiconductor properties

melt

crystal

heater

melt

crystal

multizone

heater

(a) (b)

FIGURE 2.8 Schematic illustrations of crystal growth chambers (a) LEC

and (b) VGF.

carried out either by moving the crucible in a static temperat-

ure proﬁle or by moving the temperature proﬁle within a static

crucible. Typical Bridgman processes are the vertical Bridgman

(VB) technique and its well-known variant, the vertical gradient

freeze (VGF, FIGURE 2.8(b)) technique. Actual processes used by

commercial companies are mostly proprietary technologies based

on modiﬁcations of the classical crystal growth techniques. Both

techniques offer wide process latitude to tailor crystal properties,

such as dislocation density.

A necessary factor in crystal growth technology is control of

the stoichiometry of the GaAs melt in order to maintain its stabil-

ity. This is done by maintaining an equilibrium vapour pressure

of As, which is commonly near 1 atmosphere. Two possibilities

of achieving the As pressure are available: the use of a closed hot

wall system for the crystal growth or encapsulation of the melt with

liquid B

. In the case of the Czochralski method, B

encapsu-

lation is the best method, resulting in the well-known LEC process

(FIGURE 2.8(a)). For the Bridgman process, both methods can

be used.

Ideally, GaAs crystals are free of dislocations. However, tem-

perature gradients (the main factor) along the growth front lead to

differences in the GaAs lattice constant, which allow strains to

be built up during growth. The strains are ultimately relieved by

Semiconductor properties

forming dislocations. Accordingly, it is highly desirable for the

growth method to minimise temperature gradients to minim-

ise dislocations. Unfortunately, this ideal is only approached if

the growth rate is made uneconomically slow. When the molten

GaAs crystallises at the growth front, heat is generated due to the

thermodynamic heat of solidiﬁcation. This heat contributes to the

temperature gradient and is more problematic for faster growth

rates. Nevertheless, the Bridgman methods of growth do have the

ﬂexibility to tailor the dislocation density in this way by lowering

the temperature gradients. In the LEC growths, the presence of

the liquid B

layer at the top of the melt surrounding the GaAs

crystal sets limits for the minimum achievable temperature gradi-

ent close to this phase boundary. Consequently, LEC growths have

usually been used for faster growth, lower cost material.

The thermodynamic heat of

solidiﬁcation releases heat to the

crystal interface as the crystal grows.

This heat can lead to temperature

gradients which need time to equalize,

and therefore, a faster growth rate

unavoidably leads to higher

temperature gradients, all else being

equal.

Crystal growth techniques are still being actively pursued as

research topics. The variations on each technique that are pursued

in research often blur the distinctions generalised in this section.

Consult Reference [8] for more detail.

2.3.2 Substrate properties and device requirements

Material properties important for semi-insulating GaAs substrates

include dislocation density, high electrical resistivity, low suscept-

ibility to breakage, substrate ﬂatness and spatial uniformity of

all these properties. Dislocation density and the inﬂuence of crys-

tal growthtechniqueson dislocations were discussed in some detail

in Section 2.3.1. The resistivity is often required to be greater than

-cm. This may be achieved in a variety of ways, including

ultra-low impurity levels, careful compensation of residual donors

and acceptors and compensation by deep levels. The low impurity

levels can be hard to consistently achieve for meeting the resistiv-

ity speciﬁcation. Accordingly, Cr doping was often used in the

early days of GaAs technology as a deliberately introduced deep

impurity level in order to increase both resistivity and its uniform-

ity at high resistivity values. Since the early 1980s, however, the

use of Cr doping has largely given way to another method of com-

pensation using a native GaAs defect commonly identiﬁed as EL2.

The structural origin of EL2 has been the subject of many studies

and debates. Two competing structural descriptions of EL2 deﬁne

it as either an As

antisite defect or an As

antisite defect asso-

ciated with an As interstitial. More detail on the properties of EL2

can be found in [5]. In contrast to its structural uncertainty, much

is known about its electrical characteristics. It can be described as

a deep double donor with energy levels 0.75 and 0.54 eV above

the valence band, corresponding to neutral and positively charged

states. An important empirical fact is that EL2 is controlled by

Semiconductor properties

the stoichiometry of the melt. As-rich melts are associated with

high EL2 levels, balanced stoichiometry with stable EL2 levels,

and Ga-rich melts with low EL2 levels. Crystal growth using EL2

works especially well with growth conditions where the residual

impurities are p-type. In modern commercial crystal growth sys-

tems, C is the major impurity and growth conditions are optimised

to achieve EL2 concentrations where it compensates the expected

levels of carbon (and other impurities). Because EL2 and other

deep levels have some level of conductivity that is greater than

the intrinsic pure semiconductor, variations in EL2 across a wafer

and from tail to seed end of the boule lead to variations in res-

istivity. Another interesting fact regarding EL2 is that its spatial

distributionclosely resembles that of dislocations, perhapsbecause

excess As drives both types of defects. Since all of these types of

deep levels can inﬂuence the transient characteristics of GaAs ﬁeld

effect transistors, substrate details such as this can be important in

analysing device anomalies (Section 8.2.2).

Apart from the resistivity and the dislocation density of the

substrate, the uniformity of these properties is of great import-

ance. Both properties have signature variations across a boule and

from seed to tail, as has been noted. The presence of excess As

and the distribution of electrically active complexes like EL2 are

greatly inﬂuenced by post-growth annealing. The perfect situation

would be an extremely narrow resistivity distribution across the

axial and longitudinal extent of the boule. One annealing condi-

tion that produces material close to this desired ideal result consists

in a rather fast cooling of the crystal from the maximum temper-

ature down to room temperature. However, fast cooling results

in a situation similar to the case of rapid growth of the original

crystal. The thermal gradients associated with the rapid cooling

result in the formation of dislocations. High-dislocation-density

material, therefore, allows for a faster cooling speed than the

low-dislocation-density material, as the strain-reducing disloca-

tions have already been generated. Generally, high-dislocation

material, whether Czochralski or Bridgman, can be made with

more uniform properties. Assuming that Bridgman growth meth-

ods (VGF/VB) are utilised primarily for low-dislocation-density

substrates (Section 2.3.1), each growth method has one major

advantage and consequently one major shortcoming: VGF/VB

material has lower dislocation density and LEC material offers

greater uniformity of electrical properties, principally resistivity

but possibly also uniformity of trap-related electrical anomalies

(Sections 8.2.2 and 8.8).

FETs and HBTs are the subject of Chapters 8 and 9. Some

brief comments about performance requirements will be made in

this section in order to complete the discussion of substrate

Semiconductor properties

speciﬁcations. While manufacturers of GaAs FETs and HBTs spe-

cify many properties of GaAs substrates similarly, they generally

specify substrates somewhat differently for dislocation density and

resistivity. Similar substrate speciﬁcations might include the need

for epi-ready substrates (Section 2.4) with high-quality surfaces

and well characterised and consistent oxide layers for HEMTs

and HBTs. For HEMTs, the resistivity of the substrate can inﬂu-

ence the turn-on voltage of the device. As a result, ﬂuctuations

in the resistivity, either across the wafer or from wafer to wafer,

can cause variations in the performance of the devices. HEMT

manufacturers, therefore, specify high uniformity of substrate res-

istance. Uniform substrates are also important for HBTs, but to

a lesser extent. For HBTs, the most important substrate require-

ment is that the leakage through the substrate between different

devices must be extremely low. Low leakage can be accomplished

by using substrates with very high resistivity. Consequently, HBT

manufacturers may place higher importance on the minimum

substrate-resistivity speciﬁcation than on its overall variation.

This is but one example showing why HBT manufacturers often

prefer VGF/VB substrates and HEMT manufacturers prefer LEC

material.

Other material properties that are not linked to dislocation dens-

ity are similar for Czochralski and Bridgman methods of growth.

Impurity concentrations, for example, are determined by the

equipment quality and skill of the people stafﬁng the equipment.

Much of the art in crystal growth is related to the scale-up from

one generation of substrate diameters to the next. In 2003, the

market is using a mixture of 100 and 150 mm (4 and 6 inch) dia-

meter wafers, with most major users at or moving to 150 mm. In

the future, a need for even larger diameter wafers will develop.

The growth of 200 mm wafers has already been demonstrated.

Preliminary research at this level indicates that the main ideas

presented in this section remain valid at 200 mm. GaAs electron-

ics suppliers can continue to expect to have choices between LEC

and VGF/VB substrates that they can specify based on the needs

of future generations of FETs and HBTs. As with any signiﬁcant

scale-up, the processing technology required to produce 200 mm

diameter wafers will again be very challenging for the substrate

suppliers.

2.4 EPITAXY

Epitaxial growth techniques involve the growth of the active (those

that are part of the device) semiconductor ﬁlms, usually less than

1% of the total substrate thickness, for a device of interest on

Semiconductor properties

a suitable substrate. The use of epitaxial techniques allows more

ﬂexibility in the growth and placement of semiconducting layers

and dopants than is achieved by other techniques such as bulk

crystal growth, ion implantation and diffusion. Bandgap engin-

eering becomes possible by choosing an arrangement of different

semiconductor layers so that the bandgap along the growth direc-

tion is tailored to achieve certain desired properties. The substrate

provides a template, usually of the same crystal structure and lat-

tice constant (atomic spacing), for high-quality crystalline growth.

For example, GaAs on GaAs, InGaAs on InP and SiGe on Si

are all common types of epitaxy along with many other variants.

Elemental constituents of the ﬁlm to be grown are brought into

contact with the substrate surface at elevated temperatures under

conditions optimised for the particular growth technique. Impurity

dopants may be introduced with the elemental constituents to dope

particular layers. Generally, the quality of the epitaxial layers is

much higher than that of the underlying substrate. Although crys-

tal defects in the substrate can propagate into an epitaxial layer,

they tend to diminish in number as the growth continues. For this

reason, active layers of a device are normally grown only after

growth of a suitable thickness of a “buffer” layer that ﬁlters out

defects.

Epitaxial growth involves the optimisation of layer quality by

manipulation of the experimental conditions available with a par-

ticular technique. It is very much an art because direct links

between experimental techniques and the ﬁnal result are often

difﬁcult and costly to prove. The starting surface condition of

the substrate is critically important (Chapter 3). Surfaces are

often terminated by a different structural arrangement of atoms

than in bulk crystals because dangling bonds (due to a missing

atom at the other end of the bond) have higher energy levels.

To lower their energy, surfaces are terminated by reconstruction

or incorporation of impurities, most often those commonly in

the atmosphere (oxygen and carbon). Ex-situ and in-situ clean-

ing (often high-temperature anneals to desorb several monolayers

from the surface) are utilised to make a reproducible starting condi-

tion for repeatable, high-quality growth. Today, most of the ex-situ

surface treatments have become the responsibility of the substrate

suppliers, who provide “epi-ready” substrates.

Epitaxial growth is often performed on a substrate that is cut

so that the crystal surface is several degrees away from a major

crystal plane. On GaAs, for example, a 2

◦

miscut from the [100]

plane is used to give better morphology.

Most of the methods of epitaxial optimisation depend on the

particular growth technique used. Molecular beam epitaxy (MBE)

and metal-organic chemical vapour deposition (MOCVD) are the

Semiconductor properties

major techniques in use today. Older techniques have been largely

phased out (liquid-phase epitaxy or LPE) or morphed into other

techniques. Chloride vapour-phase epitaxy (VPE) has given way

to MOCVD for most GaAs growth.

2.4.1 Molecular beam epitaxy

MBE is an ultra-high-vacuum technique (base pressure near

−10

torr). In its classic form, it involves equipment that sends a

ﬂux of atoms to a heated substrate where epitaxial growth occurs.

The atom ﬂuxes typically come from heated crucibles that evap-

orate solid sources in a vacuum. The ﬂux of atoms is directed to a

sample by an oriﬁce in the source crucible which can be switched

on and off by a shutter. Each atom ﬂux is controlled by the tem-

perature of the crucible through often painstaking calibrations. An

MBE growth chamber is shown in FIGURE 2.9.

The atoms reach the heated substrate and most of them stick

on the surface, where they diffuse around until they ﬁnd a lattice

site or the edge of a two-dimensional “island” where they can

incorporate into the lattice. The key to good growth is to heat the

substrate sufﬁciently such that good atomic mobility occurs on

the surface without excessive desorption of the atoms. Of course,

every rule has its exception, and sometimes one desires growth

FIGURE 2.9 A picture of a research MBE growth chamber.

Semiconductor properties

under conditions of low surface mobility (an example will be given

later in this section).

Generally the growth rate is deﬁned by the ﬂux of one or two

of the atoms and the other(s) are kept under excess ﬂux condi-

tions. Gallium and arsenic atoms are asymmetric in the sense that

As is much more easily desorbed than Ga and one must main-

tain a high V/III ratio during growth. In general, the As ﬂux must

be maintained during growth interruptions or during initial sur-

face treatments so that the lattice does not begin to decompose.

The same is true of the P-based semiconductors.

During the growth, progress is monitored by a variety of dia-

gnostic tools. Electron diffraction (by a technique called reﬂection

high-energy electron diffraction or RHEED) can be used during

growth to monitor the periodicity of the two-dimensional surface

as a quality metric. When the periodicity is high, the diffraction

spots are bright. The order observed in the RHEED pattern can

indicate a variety of surface conditions, especially during the initial

substrate cleaning step, when surface reconstructions and con-

taminants can be numerous and complex. MBE growth proceeds

ideally as a layer by layer growth. During the completion of a

layer, the RHEED spots are brightest and during an approximate

half layer completion, they are the dimmest. RHEED intensity

oscillations are used to “count” layers during growth and provide

either real-time growth rate feedback or calibration.

Another common in-situ diagnostic is optical reﬂectance. The

intensity of near-normal-incidence reﬂected light can be ana-

lysed for periodic structures that are common in optical devices

but reﬂectance can be used during special calibration runs

for electronic devices as well. Real-time growth-rate inform-

ation about individual layers comes out of this analysis. An

MBE chamber will have other diagnostics as well. See refer-

ences [9,10] for more details. Samples are also analysed ex-situ

(Section 2.5).

Because MBE is an ultra-high-vacuum technique and due to

the sheer size of its components, it is fairly time consuming to

initially bring the chamber to the desired vacuum. A bake-out

near 200

◦

C is required to “outgas” the interior surfaces of the

chamber so that they will not be sources of gases at the 10

−7

−8

torr level. This step can take around a week. In addition,

source material that has been vented to atmosphere must be condi-

tioned so that impurities adsorbed on the source material surfaces

do not become incorporated into and degrade the semiconductor.

Source conditioning is extremely time consuming as well. In order

to keep vent time to a minimum, MBE machines have fairly large

sources that take months or years to be consumed. Since venting

and preparing a chamber is so time consuming, MBE machines