468 DIFFUSION PROCESSES IN ADVANCED TECHNOLOGICAL MATERIALS
The bottom via areas estimated from FIB images are 0.13 0.12, 0.18 0.18,
0.25 0.20, and 0.65 0.23 mm
2
for 0.13-, 0.18-, 0.28-, and 0.73-mm-wide
lines, respectively. The variations in the values of t
1
are partly due to
the variations of the bottom via current densities, statistical error, and error
generated when measuring the via bottom Cu areas. Also, in this sample set,
error could have been generated by the lithography resolution when
attempting to pattern sub-0.18-mm-wide lines. The current density j
Line
in the
lines was 30 mAmm
2
, while via bottom current densities j
via
were estimated
to be 77, 62, 60, and 50 mAmm
2
for 0.13-, 0.18-, 0.28-, and 0.73-mm-wide
lines, respectively. The dotted lines are the mean values of t
1
and t
2
together
with their uncertainties. Comparing the data obtained from Fig. 9.42 and
Fig. 9.44(b), a slightly lower value of a
1
in CuSilK (0.2) than in CuSiO
2
(0.5) was obtained, which may be attributed to the different thermal expan-
sion mismatch between CuSiLK and CuSiO
2
. Figure 9.45(a) is a FIB
image of a tested sample in the first-failure group with a 0.13-mm-wide line.
Figure 9.45(b) and (c) shows serial images of the t
1
group from a 0.73-mm-
wide line taken 0.3 mm apart. In all three images, voids are observed at the
bottom of the Cu via, although via bottom voids are reduced in the CuSilK
dielectric compared to those in CuSiO
2
structures.
The electromigration lifetime of a dual-damascene line connected to
a completely blocking boundary W line with various Cu via sizes and
linewidths can be reasonably represented by a bimodal function. The
dominant Cu mass motion is along the Cu/dielectric interface. The first-
failure group had void formation at the via bottom and was found to be a
function of metal line thickness divided by the current density at the bot-
tom of the via or bottom via area divided by linewidth. The results from
stressing 0.13- to 0.90-mm-wide dual-damascene Cu lines are consistent
with our proposed model and suggest the importance of the via size used
in Cu interconnections, especially in wide lines.
9.12 Short-Length Effect
Atwo-level Cu interconnect structure, M1V1M2, was used for this
study.
[122]
Figure 9.46(a) and (b) shows the schematic diagrams of the test
structure. The thicknesses of M1 and M2 are 0.31 and 0.35 mm, respec-
tively. M1 is 3 mm wide and 12 mm long. M2 consists of one 0.21-mm-
wide fine test line and two 3-mm-wide lines on either side of the test line.
The fine M2 is 375 mm long. Each end of the 0.21-mm-wide M2 connects
to one end of the M1 through a V1 via. The top and bottom diameters of
the V1 via are 0.35 and 0.2 mm, respectively. The other end of the M1 is
connected to the 3-mm-wide M2 using three 3-mm-long V1 slots. The
widths of the top and bottom V1 slots are 0.46 and 0.2 mm, respectively.
The Cu M2 was passivated with SiN
x
SiO
2
. A dc current of 1.6 mA was