Power electronic handbook

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612 Y. M. Lai

−V

p(pk)

−I

p(pk)

Control

T/2

T/2+DT

−

(a)

(b)

FIGURE 23.26 A simpliﬁed half-bridge regulator: (a) circuit and (b) the associated waveforms.

23 Power Supplies 613

Note that the multiplier of 2 appears in Eq. (23.66) because

of the two alternate half cycles. Solving Eq. (23.66) for V

we have

D (23.67)

The output power P

is given by

= V

= ηP

= η

p(avg)

(23.68)

p(avg)

ηV

(23.69)

where I

p(avg)

has the value of the primary current at the center

of the rising or falling ramp. Assuming the reaction current



reﬂected from the secondary is much greater than the mag-

netizing current, then the maximum collector currents for Q

and Q

are given by

C(max)

= I

p(avg)

ηV

max

(23.70)

As mentioned, the maximum collector voltages for Q

and

at turn off are given by

C(max)

= V

i(max)

(23.71)

In designing half-bridge regulators, the maximum duty cycle

can never be greater than 50%. When both the transistors

are switched on simultaneously, the input voltage is short-

circuited to ground. The series capacitors C

and C

provide

a dc bias to balance the volt–second integrals of the two

switching intervals. Hence, any mismatch in devices would

not easily saturate the core. However, if such a situation arises,

a small coupling capacitor can be inserted in series with the

primary winding. A dc bias voltage proportional to the volt–

second imbalance is developed across the coupling capacitor.

This balances the volt–second integrals of the two switching

intervals.

One problem in using half-bridge regulators is related to

the design of the drivers for the power switches. Speciﬁcally,

the emitter of Q

is not at ground level, but is at a high ac

level. The driver must therefore be referenced to this ac level.

Typically, transformer-coupled drivers are used to drive both

switches, thus solving the grounding problem and allowing the

controller to be isolated from the drivers.

The half-bridge regulator is widely used for medium-power

applications. Because of its core-balancing feature, the half-

bridge becomes the predominant choice for output power

ranging from 200 to 400 W. Since the half-bridge is more

complex, for application below 200 W, the ﬂyback or forward

regulator is considered to be a better choice and more cost-

effective. Above 400 W, the primary and switch currents of the

half-bridge become very high. Thus, it becomes unsuitable.

23.5.4 Full-bridge Regulators

The full-bridge regulator is yet another form of isolated for-

ward regulator. Its performance is improved over that of the

half-bridge regulator because of the reduced peak collector

current. The two series capacitors that appeared in half-bridge

circuits are now replaced by another pair of transistors of the

same type. In each switching interval, two of the switches are

turned on and off simultaneously such that the full input volt-

age appears at the primary winding. The primary and the

switch currents are only half that of the half-bridge for the

same power level. Thus, the maximum output power of this

topology is twice that of the half-bridge.

Figure 23.27 shows the basic conﬁguration of a full-bridge

regulator and the associated steady-state waveforms. Four

power switches are required in the circuit. The power switches

and Q

turn on and off simultaneously in one of the half

cycles. Q

and Q

also turn on and off simultaneously in the

other half cycle, but with opposite phase as Q

and Q

. This

produces a square-wave ac with a value of ±V

at the primary

winding of the transformer. Like the half-bridge, this voltage

is stepped down, rectiﬁed, and then ﬁltered to produce a dc

output voltage. The capacitor C

is used to balance the volt-

second integrals of the two switching intervals and prevent the

transformer from being driven into saturation.

Under steady-state conditions, the operation of the full-

bridge is similar to that of the half-bridge. When Q

and Q

turn on, the voltage across the secondary winding is

(23.72)

Neglecting diode voltage drops and losses, the voltage across

the output inductor is then given by

−V

(23.73)

In this interval, the inductor current I

increases linearly at

the rate of



−V



(23.74)

614 Y. M. Lai

−V

)

p(pk)

Control

T/2

T/2+DT

−

(a)

(b)

FIGURE 23.27 A simpliﬁed full-bridge regulator: (a) circuit and (b) the associated waveforms.

23 Power Supplies 615

At the end of Q

and Q

on-time, I

reaches a value which

is given by

L1(pk)

= I

(0) +



−V



DT (23.75)

During the interval , I

decreases linearly at the rate of

(23.76)

The next half cycle repeats with Q

and Q

on and the circuit

operates in a similar manner as in the ﬁrst half cycle.

Again, as in the half-bridge, the output voltage can be found

from the time integral of the inductor voltage over a time equal

toT. Thus, we have

= 2 ×











−V



dt +

+DT



−V







(23.77)

Solving Eq. (23.77) for V

, we have

D (23.78)

The output power P

is given by

= ηP

= ηV

p(avg)

(23.79)

p(avg)

ηV

(23.80)

where I

p(avg)

has the same deﬁnition as in the half-bridge case.

Comparing Eq. (23.80) with Eq. (23.69), we see that the

output power of a full-bridge is twice that of a half-bridge

with same input voltage and current. The maximum collector

currents for Q

, and Q

are given by

C(max)

= I

p(avg)

ηV

max

(23.81)

Comparing Eq. (23.81) with Eq. (23.70), for the same output

power, the maximum collector current is only half that of the

half-bridge.

As mentioned, the maximum collector voltage for Q

and

at turn off is given by

C(max)

= V

i(max)

(23.82)

The design of the full-bridge is similar to that of the half-

bridge. The only difference is the use of four power switches

instead of two in the full-bridge. Therefore, additional drivers

are required by adding two more secondary windings in the

pulse transformer of the driving circuit.

For high power applications ranging from several hundred

to thousand kilowatts, the full-bridge regulator is an inevitable

choice. It has the most efﬁcient use of magnetic core and

semiconductor switches. The full-bridge is complex and there-

fore expensive to build, and is only justiﬁed for high-power

applications, typically over 500 W.

23.5.5 Control Circuits and Pulse-width

Modulation

In previous subsections, we presented several popular voltage

regulators that may be used in a switching mode power supply.

This section discusses the control circuits that regulate the

output voltage of a switching regulator by constantly adjusting

the conduction period t

or duty cycle d of the power switch.

Such adjustment is called pulse-width modulation (PWM).

The duty cycle is deﬁned as the fraction of the period during

which the switch is on, i.e.

d =

off

(23.83)

where T is the switching period, i.e. t

off

= T −t

. By adjusting

either t

or t

off

, or both, d can be modulated. Thus, PWM

controlled regulators can operate at variable frequency as well

as ﬁxed frequency.

Among all types of PWM controllers, the ﬁxed frequency

controller is by far the most popular choice. There are

two main reasons for their popularity. First, low-cost ﬁxed-

frequency PWM IC controllers have been developed by various

solid-state device manufacturers, and most of these IC con-

trollers have all the features that are needed to build a

PWM switching power supply using a minimum number

of components. Second, because of their ﬁxed-frequency

nature, ﬁxed-frequency controllers do not have the prob-

lem of unpredictable noise spectrum associated with vari-

able frequency controllers. This makes EMI control much

easier.

There are two types of ﬁxed-frequency PWM controllers,

namely, the voltage-mode controller and the current-mode

controller. In its simpliﬁed form, a voltage-mode controller

616 Y. M. Lai

consists of four main functional components: an adjustable

clock for setting the switching frequency, an output voltage

error ampliﬁer for detecting deviation of the output from the

nominal value, a ramp generator for providing a sawtooth sig-

nal that is synchronized to the clock, and a comparator that

compares the output error signal with the sawtooth signal. The

output of the comparator is the signal that drives the controlled

switch. Figure 23.28 shows a simpliﬁed PWM voltage-mode

controlled forward regulator operating at ﬁxed frequency and

its associated driving signal waveform. As shown, the duration

of the on-time t

is determined by the time between the reset

of the ramp generator and the intersection of the error voltage

with the positive-going ramp signal.

The error voltage v

is given by



1 +



REF

−

(23.84)

PWM output

Driving signal

Driver

Error voltage V

Comp

Sawtooth

Error amplifier

REF

−

(a)

(b)

FIGURE 23.28 A simpliﬁed voltage-mode controlled forward regulator: (a) circuit and (b) the associated driving signal waveform.

From Eq. (23.84), the small-signal term can be separated

from the dc operating point by

v

=−

v

(23.85)

The dc operating point is given by



1 +



REF

−

(23.86)

Inspecting the waveform of the sawtooth and the error

voltage shows that the duty cycle is related to the error

voltage by

d =

(23.87)

where V

is the peak voltage of the sawtooth.

23 Power Supplies 617

Hence, the small-signal duty cycle is related to the small-

signal error voltage by

d =

v

(23.88)

The operation of the ﬁxed-frequency voltage-mode con-

troller can be explained as follows. When the output is lower

than the nominal dc value, a high error voltage is produced.

This means that v

is positive. Hence, d is positive. The

duty cycle is increased to cause a subsequent increase in

output voltage. The feedback dynamics (stability and tran-

sient response) is determined by the operational ampliﬁer

circuit that consists of Z

and Z

. Some of the popular

voltage-mode control ICs are SG1524/25/26/27, TL494/5, and

MC34060/63.

The current-mode control makes use of the current infor-

mation in a regulator to achieve output voltage regulation. In

its simplest form, current-mode control consists of an inner

loop that samples the inductance current value and turns the

switches off as soon as the current reaches a certain value set by

the outer voltage loop. In this way, the current-mode control

achieves faster response than the voltage mode. There are two

types of ﬁxed-frequency PWM current-mode control, namely,

the peak current-mode control and the average current-mode

control.

In the peak current-mode control, no sawtooth generator

is needed. In fact, the inductance current waveform is itself a

sawtooth. The voltage analog of the current may be provided

by a small resistance, or by a current transformer. Also, in

practice, the switch current is used since only the positive-

going portion of the inductance current waveform is required.

Figure 23.29 shows a peak current-mode controlled ﬂyback

regulator.

In Fig. 23.29, the regulator operates at ﬁxed frequency. Turn

on is synchronized with the clock pulse, and turn off is deter-

mined by the instant at which the input current equals the

error voltage V

Because of its inherent peak current-limiting capability, the

peak current-mode control can enhance reliability of power

switches. The dynamic performance is improved because of the

use of the additional current information. One main disadvan-

tage of the peak current-mode control is that it is extremely

susceptible to noise, since the current ramp is usually small

compared to the reference signal. A second disadvantage

is its inherent instability property at duty cycle exceeding

50%, which results in sub-harmonic oscillation. Typically, a

compensating ramp is required at the comparator input to

eliminate this instability. The third disadvantage is that it has a

non-ideal loop response because of the use of the peak, instead

of the average current sensing.

Figure 23.30 shows an average current-mode controlled ﬂy-

back regulator. In the circuit, a PWM modulator (instead

Driver

Latch

Comp

Error voltage V

Error amplifier

REF

Clock

−

(a)

S,Clock

Driving signal

(b)

FIGURE 23.29 A simpliﬁed peak current-mode controlled ﬂyback

regulator: (a) circuit and (b) the associated waveforms.

of a clocked SR latch in the peak current-mode control)

is employed to compare the current error to an externally

generated sawtooth signal to formulate the desired control

signal. The main advantages of this method over the peak

current-control are that it has excellent noise immunity prop-

erty; it is stable at duty cycle exceeding 50%; and it provides

good tracking of average current. However, since there are

three compensation networks (Z

, Z

, and Z

), the analysis

618 Y. M. Lai

Driver

Sawtooth

PWM

Comp

Error voltage V

REF

−

FIGURE 23.30 A simpliﬁed average current-mode controlled ﬂyback regulator: (a) circuit and (b) the associated waveforms.

and optimal design of these networks are non-trivial. This is

a major obstacle for adopting the average current mode

control.

It should be noted that current-mode control is particu-

larly effective for the ﬂyback and boost-type regulators that

have an inherent right-half-plane zero. Current-mode con-

trol effectively reduces the system to ﬁrst-order by forcing

the inductor current to be related to the output voltage, thus

achieving faster response. In the case of the buck-type regu-

lator, current-mode control presents no signiﬁcant advantage

because the current information can be derived from the out-

put voltage, and hence faster response can still be achieved

with a proper feedback network. Some of the popular current-

mode control ICs are UC3840/2, UC3825, MC34129, and

MC34065.

Further Reading

1. A.I. Pressman, Switching Power Supply Design,2

ed., New York:

McGraw-Hill, 1999.

2. M. Brown, Practical Switching Power Supply Design,2

ed., New York:

McGraw-Hill, 1999.

3. P.T. Krein, Elements of Power Electronics,1

ed., Cambridge:

Oxford University Press, 1998.

4. J.G. Kassakian, M.R. Schlecht, and G.C. Verghese, Principles of Power

Electronics,1

ed., MA Reading: Addison-Wesley, 1991.

5. G. Chryssis, High-Frequency Switching Power Supplies,1

ed.,

New York: McGraw-Hill, 1984.

6. M.H. Rashid, Power Electronics – Circuits, Devices, and Applications,

ed., New Jersey: Prentice-Hall, 1993.

7. T.L. Floyd and D. Buchla, Fundamentals of Analog Circuits,1

ed.,

New Jersey: Prentice-Hall, 1999.

Uninterruptible Power Supplies

Adel Nasiri, Ph.D.

Power Electronics and Motor Drives

Laboratory, University of

Wisconsin-Milwaukee, 3200

North Cramer Street, Milwaukee

Wisconsin, USA

24.1 Introduction .......................................................................................... 619

24.2 Classiﬁcations ........................................................................................ 619

24.2.1 Standby UPS • 24.2.2 On-line UPS System • 24.2.3 Line-interactive UPS

• 24.2.4 Universal UPS • 24.2.5 Rotary UPS • 24.2.6 Hybrid Static/Rotary UPS

• 24.2.7 Comparison of UPS Conﬁgurations

24.3 Performance Evaluation ........................................................................... 626

24.4 Applications........................................................................................... 627

24.5 Control Techniques................................................................................. 628

24.6 Energy Storage Devices ............................................................................ 630

24.6.1 Battery • 24.6.2 Flywheel • 24.6.3 Fuel Cell

Further Reading ..................................................................................... 632

24.1 Introduction

Power distortions such as power interruptions, voltage sags

and swells, voltage spikes, and voltage harmonics can cause

severe impacts on sensitive loads in the electrical systems.

Uninterruptible power supply (UPS) systems are used to pro-

vide uninterrupted, reliable, and high quality power for these

sensitive loads. Applications of UPS systems include medical

facilities, life supporting systems, data storage and computer

systems, emergency equipment, telecommunications, indus-

trial processing, and on-line management systems [1–3]. The

UPS systems are especially required in places where power

outages and ﬂuctuations occur frequently. A UPS provides a

backup power circuitry to supply vital systems when a power

outage occurs. In situations where short time power ﬂuctu-

ations or disturbed voltage occur, a UPS provides constant

power to keep the important loads running. During extended

power failures, a UPS provides backup power to keep the

systems running long enough so that they can be gracefully

powered down.

Most of the UPS systems also suppress line transients and

harmonic disturbances. Generally, an ideal UPS should be

able to simultaneously deliver uninterrupted power and pro-

vide the necessary power conditioning for the particular power

application. Therefore, an ideal UPS should have the follow-

ing features: regulated sinusoidal output voltage with low total

harmonic distortion (THD) independent from the changes in

the input voltage or in the load, on-line operation that means

zero transition time from normal to back-up mode and vice

versa, low THD sinusoidal input current and unity power

factor, high reliability, high efﬁciency, low EMI and acous-

tic noise, electric isolation, low maintenance, low cost, weight,

and size. Obviously, there is not a single conﬁguration that can

provide all of these features. Different conﬁgurations of UPS

systems emphasize on some of the features mentioned above.

Classiﬁcations of UPS systems are described in Section 24.2.

24.2 Classiﬁcations

24.2.1 Standby UPS

This conﬁguration of UPS system is also known as “off-line

UPS” or “line-preferred UPS” [4, 5]. Figure 24.1 shows the

conﬁguration of a typical standby UPS system. It consists of

an AC/DC converter, a battery bank, a DC/AC inverter, and

a static switch. A passive low pass ﬁlter may also be used at

the output of the UPS or inverter to remove the switching fre-

quency from the output voltage. The static switch is on during

the normal mode of operation. Therefore, load is supplied

from the AC line directly without any power conditioning.

At the same time, the AC/DC rectiﬁer charges the battery set.

This converter is rated at a much lower power rating than the

power demand of the load. When a power outage occurs or

the primary power is out of a given preset tolerance, the static

switch is opened and the DC/AC inverter provides power to

619

620 A. Nasiri

AC/DC

Rectifier/

Charger

DC/AC

Inverter

Static Switch

(Normally on)

Line

Load

Battery Bank

FIGURE 24.1 Conﬁguration of a typical standby UPS system.

the load from the battery set for the duration of the preset

backup time or till the AC line is back again. This inverter

is rated at 100% of the load power demand. It is connected

in parallel to the load and stays standby during the normal

mode of operation. The transition time from the AC line to

DC/AC inverter is usually about one quarter of the line cycle,

which is enough for most of the applications such as personal

computers. The main advantages of this topology are simple

design, low cost, and small size. On the other hand, lack of real

BatteryBattery

(a) (b)

FIGURE 24.2 Two simple topologies of AC/DC rectiﬁer: (a) full-bridge diode rectiﬁer and (b) full-bridge full controlled topology.

Battery

Load

Battery

Load

(a) (b)

FIGURE 24.3 Two simple single-phase topologies for the DC/AC inverter: (a) full-bridge and (b) half-bridge.

isolation of the load from the AC line, no output voltage regu-

lation, long switching time, poor performance with non-linear

loads, and no line conditioning are the main disadvantages of

this conﬁguration.

Different conﬁgurations of AC/DC rectiﬁers such as linear

or switching may be used in this system. To reduce the cost, a

simple diode-bridge rectiﬁer with a capacitor at the front end

is used. A full-bridge or half-bridge full controlled converter is

also used to charge the battery bank. Two typical topologies for

a single-phase UPS system are shown in Fig. 24.2. The full con-

trolled topologies can provide power factor correction (PFC)

to meet the corresponding standards. To optimize the charging

process, the charging cycle is divided into “constant current”

and “constant voltage” modes. In the constant current mode,

the converter injects a constant current into the battery till the

battery is charged up to about 95% of its capacity. After this

mode, the constant voltage mode starts that applies a constant

voltage on the battery. In this mode, the input current of the

battery declines exponentially until it is fully charged.

The purpose of the DC/AC inverter is to provide high qual-

ity AC power to the load when the static switch is opened.

A full- or half-bridge topology is used for this inverter.

Figure 24.3 shows two simple single-phase topologies for the

DC/AC inverter.

24 Uninterruptible Power Supplies 621

AC/DC

Rectifier/

Charger

DC/AC

Inverter

Static Switch

(Normally on)

Line

Load

Battery Bank

FIGURE 24.4 Typical conﬁguration of ferroresonant standby UPS system.

In some topologies of standby UPS systems, an isolating

transformer is used at the output stage of the UPS. This

topology is called ferroresonant standby UPS system. The

transformer also acts as a low pass ﬁlter that cancels out

switching frequency from the output voltage of the DC/AC

inverter. On the other hand, the transformer stores electro-

magnetic energy in the core and acts as a buffer when a power

outage occurs. For a short time, the transformer provides

power to the load and protects sensitive equipment from being

affected during the transfer time from the input AC to the UPS.

Figure 24.4 shows the conﬁguration of a ferroresonant standby

UPS system. Since the transformer is bulky and expensive, this

conﬁguration is more appropriate for high power applications.

24.2.2 On-line UPS System

Similar to standby UPS systems, on-line UPS systems also

consist of a rectiﬁer/charger, a battery set, an inverter, and a

static switch (bypass). Other names for this conﬁguration are

“true UPS,” “inverter preferred UPS,” and “double-conversion

UPS” [6, 7]. Figure 24.5 shows the block diagram of a typi-

cal on-line UPS. The rectiﬁer/charger continuously supplies

AC/DC

Rectifier/

Charger

DC/AC

Inverter

Static Switch

(Normally off)

Line

Load

Battery Bank

FIGURE 24.5 Block diagram of an on-line UPS system.

power to the DC bus. The power rating of this converter must

be designed appropriately to supply power to the load and

charge the battery bank at the same time. The batteries are

rated in order to supply full power to the load during the

backup time. The duration of this time varies in different appli-

cations. The inverter is rated at 100% of the load power since

it must supply the load during the normal mode of operation

as well as during the backup time. It is connected in series with

the load; hence, there is no transfer time associated with the

transition from normal mode to stored energy mode. This is

the main advantage of on-line UPS systems. The static switch

provides redundancy of the power source in the case of UPS

malfunction or overloading. The AC line and load voltages

must be in phase in order to use the static switch. This can

be achieved easily by a phase-locked loop control. During the

normal mode of operation, the power to the load is continu-

ously supplied via the rectiﬁer/charger and inverter. In fact, a

double conversion from AC to DC and then from DC to AC

takes place. This conﬁguration of the UPS allows good power

conditioning. The AC/DC converter charges the battery set

and also supplies power to the load via the inverter. There-

fore, it has the highest power rating in this topology, thereby