Bryan L. Programmable controllers. Theory and implementation
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rungs. The fence consists of an MCR rung with conditional inputs at the
beginning of the zone and an END rung with no conditional inputs at the end
of the zone. When the MCR rung condition is TRUE, it activates the
referenced output, allowing all rung outputs within the zone to be controlled
by their respective rung input conditions. When the MCR output is turned
OFF, it de-energizes all nonretentive (nonlatched) outputs within the zone.
A zone control last state (ZCL) instruction is similar to an MCR instruction—
it determines whether or not a group of ladder rungs will be evaluated. In this
instruction, a ZCL output with conditional inputs occurs at the start of the
fenced zone, while an END ZCL output with no conditional inputs occurs at
the end of the zone. When the referenced ZCL output is activated, the outputs
within the zone are controlled by their respective input conditions. When the
ZCL output is turned OFF, the outputs within the zone stay in their last state.
An end (END) instruction signifies the last rung of a master control relay or
zone control last state instruction. This instruction is usually unconditional
(i.e., programmed without any conditions to energize). An end instruction
reference address may or may not reference a MCR or ZCL. If a reference is
included, the END instruction will end that particular MCR or ZCL. If the
instruction does not include a reference address, it will terminate the latest
MCR or ZCL instruction.
ZONE CONTROL LAST STATE
JUMP TO
A jump to (JMP) instruction allows the control program sequence to be
altered if certain conditions exist. If the rung condition is TRUE, the jump to
coil reference address tells the processor to jump forward and execute the
target rung. The jump to address label specifies the target rung to jump to.
Using this instruction, a PLC can alter the order of execution of the control
program to execute a rung that needs immediate attention. Figure 9-55
illustrates a jump to instruction. This instruction may also be called a go to
instruction. Note that care should be exercised when jumping over timers and
counters. Jumping over timers and counters will cause the timing and
counting instructions not to be executed.
END
Like a jump to instruction, a go to subroutine (GOSUB) output instruction
also allows normal program execution to be altered if certain conditions exist.
In this instruction, if the rung condition is TRUE, the GOSUB coil reference
GO TO SUBROUTINE
ZCL
ZCL
END
JMP
GOSUB
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address tells the processor to jump to the ladder rung with a label (LBL)
instruction having the same reference number. The processor then continues
the program execution until it encounters a return coil. Each subroutine in the
program must begin with a labeled rung and end with an unconditional return
instruction. A go to subroutine instruction may also be called a jump to
subroutine (JSB) instruction.
A GOSUB instruction is very useful whenever a subroutine in the program is
either referenced by several sections of the main control program or is
referenced on a timely basis (i.e., look up analog interpretation table every 10
seconds). Subroutines are generally located at the end of the control program
and are sometimes located in an area specified by the PLC maker (see Figure
9-56). If a PLC does not have a reserved subroutine area, the user can create
one by programming a dummy rung with direct control to another dummy
rung at the end of the programmed subroutines (see Figure 9-57). For proper
programming documentation order, the subroutine area should be located at
the end of the control program.
Figure 9-55. Example of a jump to instruction.
A label (LBL) instruction identifies the ladder rung that is the target
destination of a jump to or GOSUB instruction. The label instruction
reference number must match that of the jump to or GOSUB instruction with
which it is used. A label instruction does not contribute to logic continuity
LABEL
Main Control
Program
Main Control
Program
Main Control
Program
10 11 JMP 100
100 12 13 300
This section
is bypassed—
logic not
solved
If contacts 10 and 11
close, program execution
jumps to the rung labeled
LBL 100 and continues.
LBL
LBL
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Figure 9-56. PLC with assigned subroutines at the end of the program.
Figure 9-57. User-created subroutine area.
Main Control
Program
Main Control
Program
Subroutine #1
Subroutine #2
10 GOSUB 1
11 GOSUB 2
1 300
RET
RET
If contact 10 closes, subroutine #1
is executed. Once finished, the
processor returns to the instruction
that follows. If contact 11 closes,
subroutine #2 is executed.
The EOS (end-of-scan) signal is
triggered at the end of the control
program before the subroutine
area starts.
LBL
2 400
LBL
Main Control
Program
Subroutine #1
Subroutine #2
GOTO 100
The unconditional GOTO 100
instruction jumps control to LBL
100, which is the last instruction
in the program. Each subroutine
must have unique LBL and RET
instructions.
EOS occurs after the dummy
output (200) is executed.
100 200
LBL
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snoitcurtsnIcitemhtirA
)atadretsigerhtiwsnoitcnuflacitamehtammrofrepotsCLPwollaoT:esopruP(
noitcurtsnIlobmySnoitcnuF
reddaL—noitiddA
owtniderotsseulavehtsddA
sretsiger
kcolB—noitiddADDA
owtniderotsseulavehtsddA
sretsiger
reddaL—noitcartbuS
niderotsseulavehtstcartbuS
sretsigerowt
kcolB—noitcartbuSBUS
niderotsseulavehtstcartbuS
sretsigerowt
reddaL—noitacilpitluM
niderotsseulavehtseilpitluM
sretsigerowt
kcolB—noitacilpitluMLUM
niderotsseulavehtseilpitluM
sretsigerowt
reddaL—noisiviD
seulavehtfotneitouqehtsdniF
sretsigerowtni
kcolB—noisiviDVID
seulavehtfotneitouqehtsdniF
sretsigerowtni
kcolB—tooRerauqSRQS
afotoorerauqsehtsetaluclaC
eulavretsiger
Table 9-7. Arithmetic instructions.
RETURN
A return (RET) instruction terminates a ladder subroutine and is pro-
grammed with no conditional inputs. When the control program encounters
this instruction, it returns to the main program, going to the ladder rung
immediately following the GOSUB instruction that initiated the subroutine.
Normal program execution continues from that point. Each subroutine must
have a return instruction.
9-10 ARITHMETIC INSTRUCTIONS
Arithmetic instructions in a PLC include the basic four operations of
addition, subtraction, multiplication, and division. In addition to these four
math functions, large PLCs may also include square root operations. Table
9-7 lists these typical arithmetic instructions and their symbols.
and, for all practical purposes, is always logically TRUE. This instruction is
always the first condition instruction in the referenced rung. A label instruc-
tion referenced by a unique address can only be defined once in a program.
ADD
+
SUB
–
MUL
×
DIV
÷
RET
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Figure 9-58. (a) Coil, (b) contact, and (c) block format arithmetic instructions.
Like other instructions, arithmetic instructions may be in either the basic
ladder format or the functional block format; however, operation in either
format is essentially the same. Figure 9-58 illustrates these formats. Most
arithmetic instructions require three reference registers, which define the two
operand registers and the destination register of the operation. Some instruc-
tions, such as multiplication and division, may use four registers. Most
arithmetic operations in a PLC require only single-precision arithmetic,
meaning that the values of the operands and the result can be held in one
register each. If operations dealing with larger numbers are required, a PLC
may offer double-precision arithmetic instructions. Double precision
means that the system uses double the number of registers to hold the
operands and result, because it must store larger numbers. For example, a
double-precision addition instruction would use a total of six registers, two
for each operand and two for the result.
As discussed earlier, a register can hold a maximum value of 65,535 in 16
bits (all 1s) if there is no sign bit. If the most significant bit is used as the sign
bit, then a register may hold a maximum value of +32,767 and a minimum
value of –37,767. If the result value of the operation is larger than the value
a register can hold, an overflow condition will exist, and the instruction will
turn ON an overflow bit or output. The numerical format used in math
operations will vary depending on the PLC but is usually three, four, or five
digits (BCD or binary). Note that in single-precision BCD, the maximum
register value is 9999 (unsigned) or ±999 (signed).
In the following discussion, we will present arithmetic instructions in both
ladder and block formats to familiarize you with the differences between
them. Note that the ladder format may require other ladder data transfer
ADD
(a)
+
(b)
Reg X + Reg Y = Reg Z
Reg X
+
Reg Y
=
Reg Z
ADD
Control
Output
(c)
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ADDITION—LADDER
Figure 9-60. Arithmetic operations performed in block form.
instructions to obtain the arithmetic operands. In functional block format,
some manufacturers offer the ability to “cascade” block functions (see Figure
9-59). Cascading is very useful when dealing with multiple arithmetic
operations, since one instruction will activate the next one when finished.
Other manufacturers allow arithmetic operations to be performed in block
form (see Figure 9-60); that is, using blocks of several contiguous registers as
the operands and storing the results in another block of registers.
Figure 9-59. “Cascading” allows several functional block arithmetic operations to be
performed sequentially.
The addition (ADD) ladder instruction adds the values stored in two refer-
enced memory locations. Different controllers access these values differently.
Some instruction sets use a get (GET) data transfer instruction to access the
two operand register values (see Figure 9-61), while others simply reference
the two registers using contact symbols (see Figure 9-58b). The processor
stores the sum of the values in the register referenced by the ADD coil. If the
addition operation is enabled only when certain rung conditions are TRUE,
then the input conditions should be programmed before the addition rung.
One bit in the addition result register usually signals an overflow condition.
10 100
Reg 1000
+
Reg 1001
=
Reg 1002
ADD
Reg 1002
x
Reg 2000
=
Reg 2001
MUL
Reg 2001
÷
K33
=
Reg 2002
DIV
Note: K33 in the division block indicates a constant of 33.
10 100
Length = 4
Reg 1000
+
Reg 1200
=
Reg 1400
ADD
Note: The contents of registers 1000, 1001, 1002, and 1003
will be added to registers 1200, 1201, 1202, and 1203. The
results will be stored in registers 1400, 1401, 1402, and 1403.
ADD
+
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Figure 9-61. Ladder format addition.
ADDITION—BLOCK
An addition (ADD) functional block adds two values stored within the
controller and places the sum in a specified register. The operand values can
be fixed constants, values contained in I/O or holding registers, or variable
numbers stored in any memory location. Figure 9-62 illustrates a typical
addition functional block.
Figure 9-62. Addition functional block.
Reg X
A ADD
GET
Reg Y Reg Z
GET
+
If A closes, the contents of register X and register Y are added
and stored in register Z. If A does not close, no addition is
performed. If contact A was omitted, the addition would be
performed in every scan.
Reg 1000
+
Reg 1001
=
Reg 2000
ADD
Control
Enable or
DoweOutput
10
ADD
10
100
101
Reg 1000
+
Reg 1001
=
Reg 2000
OF
EN
Enable
Overflow
To control
other logic
973
119
1000
Reg
1001
01 9 2 2000
Storage Area
Contents in BCD
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A control line enables the operation of an addition block. When the rung
conditions are TRUE, the processor performs the addition function. In the
block shown in Figure 9-62, register 1000 and register 1001 can be preset
values, storage registers, or I/O registers. Each time an OFF-to-ON transition
enables the control line, the instruction adds the values in these two registers
and places the result in register 2000. The done, or enable, output coil
indicates that the operation has been completed. This output remains ON as
long as the control line is TRUE. An overflow of the addition operation
energizes the overflow output of the block. If the operation overflows, some
PLCs will clamp, or store, the results at the maximum value that the register
can hold. Others will store the difference between the maximum count value
and the actual overflow value.
Some controllers use double-precision addition when working in block
format (see Figure 9-63). This operation is identical to simple ladder
addition, but the PLC uses two registers each to hold the operands and two
registers to store the result.
EXAMPLE 9-8
In Figure 9-64, two ingredients are added to a reactor tank for mixing.
Analog input modules, which provide 12-bit information in BCD, send
data about the two ingredients’ flows to the PLC. The values are stored
in registers 1000 and 1001. Implement instructions to keep track of
the total amount of the combined ingredients, so that this information
can be displayed on a monitor for the operator.
Figure 9-63. Double-precision addition block
.
10
Reg 1000
+
Reg 1001
=
Reg 2000
Overflow
Done
1999 9998
R 2000 R 2001
19,999,998
999 9999
R 1100 R 1101
9,999,999
999 9999
R 1000 R 1001
9,999,999
ADD
+
=
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Figure 9-64. Flow of two ingredients into a reactor tank.
Figure 9-65. Solution to Example 9-8.
SOLUTION
One register can hold the total of both ingredients after the addition of
the two ingredients’ flows. Figure 9-65 shows the use of an ADD
instruction to store the BCD result in register 2000. Note that this ADD
instruction is always active.
SUBTRACTION—LADDER
The subtraction (SUB) ladder instruction subtracts the values stored in two
registers. As in an addition instruction, if the rung is enabled, the subtraction
operation occurs. A GET data transfer instruction usually accesses the two
Ingredient 1 Ingredient 2
Flow A
Reg 1000
Flow B
Reg 1001
Reg 1000
+
Reg 1001
=
Reg 2000
Reg 1000 = Ingredient A
Reg 1001 = Ingredient B
Reg 2000 = Sum of ingredients A and B
ADD
100
SUB
–
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SUBTRACTION—BLOCK
The subtraction (SUB) functional block, as in the ladder format subtraction
instruction, finds the difference between two values and stores the result in a
register. Figure 9-67 shows a typical subtraction functional block.
Figure 9-67. Subtraction functional block.
Figure 9-66. Ladder format subtraction instruction.
The control input in a subtraction block operates the same way as in an
addition block. When the rung condition is logic 1, the controller performs the
block operation. Three registers hold the data during the operation. The values
that these registers can hold vary in format and may or may not include a sign
bit. For example, referring to Figure 9-67, register 1000 could contain 9009
decimal and register 1001 could hold –10,020. The result of this operation
would be +19,029 [9009 – (–10,020)], which would be stored in register 2000.
Since the formats for subtraction vary, sometimes the result register may not
registers used by a SUB instruction. The subtraction result register will
usually have an underflow bit to represent a negative result. Figure 9-66
shows a rung with a SUB instruction.
Reg: 1000
10
SUB
100
GET
Reg: 1001 Reg: 2000
GET
—
1000
Reg
1001
2000
Storage Area
Contents in
Decimal (Binary)
24875
1266
23609
If contact 10 closes, the value in register 1001 is subtracted from the
value in register 1000 (Reg 1000 – Reg 1001) and the result is stored in
register 2000. If contact 10 does not close, no subtraction is performed.
Reg 1000
–
Reg 1001
=
Reg 2000
SUB
Control Output Done/
Enable