Bryan L. Programmable controllers. Theory and implementation
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1029
Index
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hexadecimal number system 40–41
IEC 1131 standard 374–375
IEC 1131-3 programming standard
data functions 375
data variable types 375–376, 378
function blocks 376
IEC 1131-3–like languages 432–438
instructions 375–376
languages 16, 375, 380–392
function block diagram 375, 381–384, 392
instruction list 375, 384, 392
ladder diagram 375, 380, 392
sequential function chart 375, 387–392
structured text 375, 386–387, 392
programming guidelines 439
programming notation 392–394
software systems 429–435
troubleshooting guidelines 439, 440–441
variable declaration 377–380, 543–544
variable scope 376
IEEE network standards 870–871
IEEE 802.3 870–871
IEEE 802.4 871
IEEE 802.5 871
IL. See instruction list
I mode controllers. See integral controllers
increment instruction 343
individual control 972
inference engine 778
input device 71
input instructions. See instructions
input interfaces
analog 189–191, 196–198
discrete 150–162
AC/DC 151–153
DC 153–155
isolated 156–157
register/BCD 158–162
TTL 157–158
input/output system. See I/O system
input table 121
input voltage 99–101
instruction list 375, 384, 392
instructions
analog
input 187–188
output 201–203
arithmetic 322–334
counter 306–307, 312–316
data manipulation 334–347
data transfer 348–358
discrete
input 147–150
output 162–164
ladder relay 289–297
network communication 363–369
program/flow control 317–322
special function 358–363
timer 306–307, 308–312
integer variables 378
integral controllers 690–692, 706–715
integral of time and absolute error tuning method. See
ITAE controller tuning method
integral time 712–713
integral windup 724, 743
intelligent I/O modules 85, 218
InterBus Loop device bus network 896
InterBus-S device bus network 886–888
interfaces. See specific type of interface
internal bit storage area 122–123
internal coil. See internal output
internal output 123, 292
internal storage address assignment document 450–
451, 542
International Electrotechnical Commission. See IEC
1131 standard
invert instruction 343
I/O address assignment document 542, 450–451
I/O bus networks 880–918
addressing 915
advantages 885–886
device bus networks 883–884, 886–898
bit-wide 894–898
byte-wide 886–894
installation 910–914
process bus networks 883–884, 899–910
protocol 884–885
I/O bus network scanner 880
I/O system 11. See also specific I/O systems
addressing 128–131, 139, 142–146, 198, 450–451
analog 186–187
discrete 138–139, 182–183
documentation 539–542
installation 942–948
intelligent interfaces 85
peripheral interfacing 260–271
programming 465–521
remote 146–147
selection 970–971
special function 218–220
specifications 927–928, 928–929, 942–948
troubleshooting 956–958
I/O table 128–131, 144
I/O update scan 87. See also scan
I/O wiring connection diagram 539–541
isolated interfaces
input 156–157
output 168–169
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Index
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isolation transformer 101, 932
ITAE controller tuning method 756–760
jump to instruction 319
knowledge AI systems 775
knowledge database 777–778
knowledge inference 781–788
knowledge representation 778–780
label instruction 320–322
ladder diagram 375, 380, 392
ladder diagram symbols. See contact symbols
ladder diagrams 24–25, 69–71. See also ladder
language
format 282–288
ladder rung matrix 285–286
ladder language 277–280. See also ladder
diagrams; specific instructions
basic 278–280
enhanced 278–280
instructions
arithmetic 322–334
counter 306–307, 312–316
data manipulation 334–347
data transfer 348–358
ladder relay 289–297
network communication 363–369
program/flow control 317–322
special function 358–363
timer 306–307, 308–312
programming 298–304
programming normally closed inputs 300–304
ladder relay instructions 289–297
examine-OFF 291
examine-ON 290
latch output coil 295
NOT output coil 293–294
one-shot output 296–297
output coil 291–293
transitional contact 297
unlatch output coil 295–296
ladder rung matrix 285–286
lag 630–631, 645–653
first-order 631, 646–650
second-order 631, 651–653
LAN. See local area networks
language. See programming languages
Laplace transforms 632–653
dead time 644–645
derivative 633–641
integral 641–644
lag 645–653
first-order 646–650
second-order 651–653
latch output coil instruction 295
LD. See ladder diagram
lead resistance compensation 226–227
leaky inputs 945–946
least significant bit 37
least significant digit 41
limit instruction 336–337
linear variable differential transformer. See LVDT
load cells 591
local area networks 848–877
access methods 857–859
collision detection 858
polling 858
token passing 858–859
advantages 850–851
communication media 860–862
data transmission techniques 856–857
definition 848–849
history 848
PLC applications 851
protocols 866–874
response time 863–864
selection guidelines 875–877
specifications 862–866
testing 874
topologies 851–856
common bus 854
master/slave bus 854
ring 854–855
star 853
star-shaped ring 855–856
troubleshooting 874
local rack 140–141
logic functions 57–64, 65
AND function 57–58
NAND gate 64
NOR gate 64
NOT function 60–64
OR function 59–60
logic matrix instruction 338–340
longitudinal redundancy check 95
loop tuning 747–766
ITAE method 756–760
software methods 764–766
Ziegler-Nichols methods
altered closed-loop 763–764
closed-loop 760–763
open-loop 751–756
LRC. See longitudinal redundancy check
LSB. See least significant bit
LVDTs 569–572, 587
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MAC. See medium access control
macrostep 391
manual programmer. See miniprogrammer
master control relay instruction 318–319, 458–462
master rack 140
master/slave bus topology 854
maximum value defuzzification method 819
mean 554–555
mean-time-between-failures study 981
measurement devices 565–599, 603–608
bridge circuits 566–569
displacement transducers 586–588
flow transducers 591–598
LVDTs 569–572
pressure transducers 588–591
thermal transducers 572–586
vibration transducers 599, 603–608
measurement errors 558–565
gross error 558
guarantee error 564–565
interpreting 560–565
propogation error 560–563
random error 558
system error 558
median 555–556
medium access control 908–909
membership functions 806–807
memory map 119
memory system 10, 82, 110–111, 133–135
and I/O interaction 127–131, 132
capacity 116–119, 133–135
selection 973–974
structure 115, 119–127
utilization 117
memory types 111–115
electrically alterable read-only memory 114
electrically erasable programmable read-only
memory 114–115
erasable programmable read-only memory 113–114
nonvolatile 111
programmable read-only memory 113
random-access memory 112
read-only memory 112
volatile 111
microprocessor 84–86. See also processor
miniprogrammer 12, 104–105, 974
mode 556
most significant bit 37
most significant digit 42
move block instruction 350
move instruction 348–350
MSB. See most significant bit
MTBF study. See mean-time-between-failures study
multidrop configuration 146
multiplexing 159–161, 171–173
multiplication instruction 330–331
multiprocessing 85
NAND gate 64
negative feedback 615
negative logic 57
network communication instructions 363–369
get node 368–369
network contact 366
network output 365
network receive 367
network send 366–367
send node 368
network contact instruction 366
network interface modules 252–253
network output instruction 365
network receive instruction 367
network send instruction 366–367
networks. See also specific network types
access methods 857–859
communication media 860–862
data transmission techniques 856–857
I/O bus networks 880–918
local area networks 848–877
protocols 866–874, 884–885
topologies 851–856, 880
nibble 37
nonstored action. See normal action
nonvolatile memory 111. See also memory types
NOR gate 64
normal action 424–426
normally closed contact instruction. See examine-OFF
instruction
normally closed inputs (programming) 300–304, 457
normally open contact instruction. See examine-ON
instruction
NOT function 60–64
NOT output coil instruction 293–295
number systems 34–41
binary number system 36–38
conversion 35–36, 41–43
decimal number system 34–36
hexadecimal number system 40–41
octal number system 38–40
octal number system 38–40
OFF-delay de-energize timer instruction 311
OFF-delay energize timer instruction 311
offset 700
ON-delay de-energize timer instruction 310
ON-delay energize timer instruction 310
one-shot output instruction 296–297
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one’s complement 44
ON/OFF controller. See two-position discrete controllers
OR convergence 411
OR divergence 410–411
OR function 59–60
orifice plate 593–597
OSI reference model 867–869
output coil instruction 291–293
output device 70
output instructions. See instructions
output interfaces
analog 201, 203–205, 207–210
discrete 165–176
AC 165–167
contact 175–176
DC 167–168
isolated 168–169
register/BCD 169–175
TTL 169
output table 122
overdamped system response 653–658
panel enclosures 922–928
parallel circuit 76
parity 93–94. See also error-checking techniques
PC. See personal computer
PD mode controllers. See proportional-derivative
controllers
peripheral interfacing 260–271
communication standards 260–261
serial communication standards 261–269
personal computer
as programming device 12, 106–108, 975
as “soft PLC” 16
versus PLC 15–16
PID bumpless auto/manual transfer 743–744
PID instruction 362–363
PID interfaces 229–233. See also proportional-
integral-derivative controllers; process control
PID mode controllers. See proportional-integral-
derivative controllers
piezoelectric transducers 603–604
PI mode controllers. See proportional-integral control-
lers
PLC
applications 17–21
architecture 10–12
definition 4
documentation 536–549
features 6–9, 26–32
history 5–6
implementation 444–465
installation 29–30, 922–948
logic 68–70
maintenance 31–32, 952–954
product ranges 22–23, 962–969
selection 962–982
start-up 948–952
system layout 922–931, 971–973
troubleshooting 31–32, 954–959
versus computer control 14–15
versus personal computer 15–16
versus relay control 13–14
P mode controllers. See proportional controllers
polling 858
positioning interfaces 233–248
continuous positioning mode 238–239, 244
encoder/counter interfaces 234–235
instructions 233
resolution 246–248
servo motor interfaces 243–248
single-step positioning mode 238–239, 244
stepper motor interfaces 235–243
positive feedback 615
positive logic 56
potentiometers 587–588
power supply 10, 11, 82, 98–103
input voltages 99–101
line tolerance 99
loading 101–103, 200, 213
specifications 931–932, 941–942
pressure transducers 588–591
Bourdon tubes 589–590
load cells 591
strain gauges 588–589
process bus networks 883–884, 899–910
Fieldbus 901–905
Profibus 906–910
wiring guidelines 913–914
process control
advanced systems 744–747
bumpless cascade control 747
cascade control 744–747
controller actions 671–676
direct-acting 621, 672–674
reverse-acting 621, 674–676
controller modes 676–744
continuous 690–744
discrete 676–690
definition 610–614, 670
Laplace transforms 632–653
dead time 644–645
derivative 633–641
integral 641–644
lag 645–653
loop tuning 747–766
PID bumpless auto/manual transfer 743–744
process dynamics 623–631
dead time 628–630, 644–645
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lag 630–631, 645–653
process gain 627–628
transfer functions 624–627, 633
transient responses 625–627
stability responses 670–671
system parameters 614–623
control variable 618–621
error 611–612, 614–618, 621
error deadband 622–623
process dynamics 623–631
dead time 628–630, 644–645
lag 630–631, 645–653
first-order 631, 646–650
second-order 631, 651–653
process gain 627–628
transfer functions 624–627, 633
transient responses 625–627
process gain 627–628
processor 10, 82, 84–86, 86–91
process variable 610. See also process control
Profibus process bus network 906–910
program coding 464–465
program/flow control instructions 317–322
end 319
go to subroutine 319–320
jump to 319
label 320–322
master control relay 318–319
return 322
zone control last state 319
programmable controller. See PLC
programmable logic controller. See PLC
programmable read-only memory (PROM) 113
programming devices 12, 104–108, 974–975
miniprogrammer 12, 104–105, 974
personal computer 12, 106–108, 975
programming languages 69, 276–281. See also IEC
1131-3 programming standard; specific languages
Boolean language 280, 369
Grafcet 281
ladder language 277–280
program scan 87. See also scan
PROM. See programmable read-only memory
propagation error 560–563
proportional band 693
proportional controllers 690–706
proportional-derivative controllers 729–736
proportional-integral controllers 715–724
parallel 716–717
series 716–717
proportional-integral-derivative controllers 736–744
protocols 866–874
IEEE standards 870–871
OSI reference model 867–869
TCP/IP protocol 872
pulse action 423–424
pulse stretcher. See fast-response module
quarter-amplitude response 749–750
rack 130, 139–146
local 140–141
master 140
remote 141, 146–147
RAM. See random-access memory
random-access memory (RAM) 112
random error 558
rate mode. See derivative controllers
read-only memory (ROM) 112
read/write memory (R/W). See random-access memory
real variables 378
reference address. See address
register/BCD interfaces
input 158–162
output 169–175
register formats 50–52
BCD 51–52
binary 51
register/word storage area 123–124
relay control (versus PLCs) 13–14
relay logic 5–6, 68–69
remote I/O system specifications 178–182
remote rack 141, 146–147. See also subsystems:
remote
remote subsystems. See subsystems: remote
repeating 717–718, 731
reset mode. See integral controllers
reset time 712–713
reset windup. See integral windup
resistance temperature detector. See RTD
resolution 190, 205, 246–248
retentive ON-delay timer instruction 312
retentive timer reset instruction 312
return instruction 322
reverse-acting controller 621, 674–676
ring topology 854–855
ROM. See read-only memory
rotate instruction 344–345
RTD input modules 228–229. See also RTDs
RTDs 573–575
rules
artificial intelligence 778–780
fuzzy logic 809–812
rung 70
safety circuitry 932–935
scaling 190–191, 209, 330–331
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scan 11, 86–91, 132
I/O update scan 87
program scan 87, 298–299
reading fast inputs 89–91
scan time 87–88
scan time 87–88
scratch pad area 120
second-order system response 631, 651–653, 653–665
critically damped 658–662
overdamped 653–658
underdamped 662–665
send node instruction 368
sequencer instruction 358–360
sequential function charts 375, 387–392
convergences 409–413
divergences 409–413
format 398–401
action 387, 419–429
levels 399
macrostep 391
step 387
transition 388, 402–403
programming 403–418
subprograms 414–418
serial communication standards 261–269
EIA RS-232C 262–265
EIA RS-422 265–267
EIA RS-485 267–268
20 mA current loop 268–269
series circuit 76
Seriplex device bus network 897–898
servo motor interfaces 243–248
set constant parameters instruction 343
set point 610
SFC. See sequential function charts
SFC action 426–429
shift instruction 344, 345
single convergence. See OR convergence
single divergence. See OR divergence
single-ended connections
input 199
output 213
single-precision arithmetic 323
single-step positioning mode 238–239, 244
sink/source configuration 153–155, 167–168
sneak paths 286
software controller tuning methods 764–766
solid flow transducers 591–592
sort instruction 357–358
special function instructions 358–363
diagnostics 361–362
PID 362–363
sequencer 358–360
special function I/O system
ASCII I/O interfaces 249–251
computer modules 251–252
fuzzy logic interfaces 255–260
network interface modules 252–253
peripheral interfacing 260–271
positioning interfaces 233–248
encoder/counter interfaces 234–235
servo motor interfaces 243–248
stepper motor interfaces 235–243
special analog interfaces 224–233
PID interfaces 229–233
RTD input modules 228–229
thermocouple input modules 226–228
weight input modules 224–225
special discrete interfaces 220–224
fast-input interfaces 220–221
fast-response interfaces 222–224
wire input fault module 221–222
specifications 178–182, 218–220
specifications 975–980
component placement 926, 926–928
electrical 929–931
environmental 926
grounding 930–931
heat 937–941
I/O 178–182, 927–928, 928–929, 942–948
electrical 178–182
environmental 182
mechanical 182
noise 935
panel enclosures 922–928
power supply 931–932, 941–942
safety 932–935
system layout 922–931
wiring 929–931
square root instruction 333–334
ST. See structured text
stable system response 670–671
stand-alone action 422–423
standard deviation 556–558
star configuration 146
star topology 853
star-shaped ring topology 855–856
step (SFC) 387
stepper motor interfaces 235–243
step response 625
step test 625
storage area 122–124
internal bit storage area 122–123
register/word storage area 123–124
storage register assignment table 455, 543
strain gauges 588–589
structured text 375, 386–387, 392
subprograms 414–418
operation 414–416
syntax 416–418
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subsystems
architecture 92, 146–147
remote 30, 146–147
subtraction instruction 327–329
sum-of-the-weights method 35
system abstract 537–538
system configuration diagram 538–539
system documentation. See documentation
system error 558
system implementation. See system programming
system layout 450, 922–931, 971–973
system memory 120
executive memory 110–111, 119
scratch pad area 120
system programming
analog I/O 492–521
control strategy 444–445
control task 444
discrete I/O 465–492
guidelines 445–446
hardwired elements 455–457
organization 446–465
program coding 464–465
special input devices 457–464
table move instruction 351–353
TCP/IP network protocol 872
thermal transducers 572–586
RTDs 573–575
thermistors 575–579
thermocouples 579–586
thermistors 575–579
thermocouple input modules 226–228. See also
thermocouples
thermocouples 579–586
thermopile 584–585
three-mode controllers. See proportional-integral-
derivative controllers
three-position discrete controllers 686–690
timer instructions 306–307, 308–312, 463–464
OFF-delay de-energize timer 311
OFF-delay energize timer 311
ON-delay de-energize timer 310
ON-delay energize timer 310
retentive ON-delay timer 312
retentive timer reset 312
token passing 858–859
transducers 189–190, 203, 565–599, 603–608
bridge circuits 566–569
displacement 586–588
flow 591–598
LVDT 569–572
pressure 588–591
thermal 572–586
vibration 599, 603–608
transfer functions 624–627, 633
transient responses 625–627
transition (SFC) 388, 402–403, 404–409
transitional contact 297
transmission control protocol/internet protocol. See
TCP/IP network protocol
transmitter 189–190
tree topology 880
truth table 58
TTL interfaces
input 157–158
output 169
turbine flow meter 597–598
20 mA current loop 268–269
twisted-pair conductors 860
two-position discrete controllers 677–686
two’s complement 45
underdamped system response 662–665
unlatch output coil instruction 295–296
unstable system response 670–671
up counter instruction 313–314
user program area 120, 126–127
variable declaration 543–544
Venturi tube 593–597
vertical redundancy check (VRC). See parity
vibration
characteristics 599–603
levels 604–608
vibration transducers 599, 603–608
volatile memory 111. See also memory types
voltage-sensitive bridge circuit 566–568
weight input modules 224–225
wire bundling 943
wire input fault modules 221–222
word 37, 115
X-OR. See exclusive-OR
Ziegler-Nichols controller tuning methods
altered closed-loop 763–764
closed-loop 760–763
open-loop 751–756
zone control last state instruction 319