Bryan L. Programmable controllers. Theory and implementation
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Figure 9-68. Subtraction block with sign outputs.
Figure 9-69. Subtraction block used to (a) read an analog input and (b) write an
analog output.
include a sign bit. In this case, the controller will provide three outputs (see
Figure 9-68): a positive result output (register 1000 greater than register
1001), an equal result output (register 1000 equal to register 1001), and a
negative result output (register 1000 less than register 1001). The block will
energize the output that corresponds to the result value. A three-output
subtraction block essentially performs a comparison function.
Some controllers allow a constant to be added to another register, through the
block function, by placing an indicator, such as the letter K, in front of the
number (e.g., K1035 = constant 1035). Controllers that do not provide I/O
transfer instructions may use subtraction blocks to transfer analog or multibit
I/O values to and from the I/O table. They do this by subtracting a constant
of 0 from the input/output data and then storing the result in the target register.
Figure 9-69 illustrates an example of a SUB block instruction used to read an
analog input and write an analog output. If contact 10 closes, the SUB
operation is executed. Register 100 specifies the reference address of the input
or output module (analog or multibit). During the reading of an input, a
constant of 0 (register 1001) is subtracted from the input module’s input value
(register 100) and the result is stored in register 1000 for use by the control
program. During the writing of an output, a constant of 0 (register 1001) is
subtracted from the value in register 1000 and the result is sent to the output
module (register 100).
Reg 1000
–
Reg 1001
=
Reg 2000
SUB
Control Output 1: Result Positive (+)
Output 2: Result Equal (=)
Output 3: Result Negative (–)
10 200
201
Reg 100
–
Reg 1001
=
Reg 1000
OF
ENControl
SUB
Register 1001 contains a
constant of 0.
Register 100 overlaps
analog input.
10 200
201
Reg 1000
–
Reg 1001
=
Reg 100
OF
ENControl
SUB
Register 1001 contains a
constant of 0.
Register 100 overlaps
analog output.
(a) (b)
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Figure 9-70. Ladder format multiplication instruction.
One or two output coils reference the two result registers in a multiplication
instruction, depending on the PLC. GET instructions access the operand
registers. If a condition must be present to enable the operation, it should be
programmed before the multiplication rung accesses the two operands. In
Figure 9-70, if contact 10 closes, the contents of registers 1000 and 1001 will
be multiplied and stored in registers 2000 and 2001.
A multiplication (MUL) ladder instruction multiplies the values from two
operand registers. It then uses two other registers to hold the result of the
multiplication (see Figure 9-70). The reason why the result is held in two
registers is that, normally, the product of two 4-digit numbers is an 8-digit
number. Some controllers provide two adjacent registers in which to store
the result.
MULTIPLICATION—LADDER
MULTIPLICATION—BLOCK
As with the multiplication ladder instruction, a multiplication (MUL) block
function uses two registers to store the result and one register to hold each of
the operands. Figure 9-71 illustrates a multiplication block, with a control line
enabling its operation.
A PLC may use double-precision for a multiplication block, meaning that
there will be twice the number of registers for the operands and result. This
allows, for example, an 8-digit BCD number to be multiplied by another 8-
digit BCD number with the result (up to 16 digits BCD) stored in four result
registers. Other controllers use scaling, in which the result of the multiplica-
Reg: 1000
10
MUL
100
GET
Reg: 1001 Reg: 2000
2001
GET
x
Contents in BCD
Result = 00339250
250
3
0
157
1000
Reg
1001
250
0
9
033
2000
2001
Storage Area
MUL
×
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Figure 9-71. Multiplication functional block.
tion is held temporarily in two registers and then multiplied by a scale value
(see Figure 9-72). For example, assume that a PLC has a 4-digit BCD format
and that registers 1000 and 1001 contain the values 9001 and 8172, respec-
tively, with a scaling value of –5 (or 10
–5
). If the controller uses scaling, it will
hold the result (73,556,172) in two result registers temporarily (as 7355 and
6172), and then multiply it by the scaling value (10
–5
), resulting in 735.56172.
Thus, the result register will contain the value 736 (rounded off). Knowing
that the result has been scaled, the user can compute the actual result, which
is 736 × 10
5
(73,600,000).
Figure 9-72. Multiplication function block with scaling.
Reg 1000
x
Reg 1001
=
Reg 2000
2001
Overflow
Done or
Enable
MUL
Control
Reg 1000
x
Reg 1001
=
Reg 2000
2001
Overflow
Enable
OF
EN
MUL
Control
SCALE
Reg: 2200
001
1
9
872
1000
Reg
1001
736
0
0
000
172
3
6
755
5
2000
2001
2200
Storage Area
Temporary Storage Registers
Mult
Store
Note: The scale value is positive
in register 2200 but interpreted
as 10
–5
by the processor.
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DIVISION—LADDER
A division (DIV) instruction finds the quotient of two numbers. This quotient
is held in two result registers and referenced by the output coil. The first result
register generally holds the integer part of the quotient, while the second result
register holds the decimal fraction part. Both operands used in a division
operation may be obtained through GET instructions. Figure 9-73 shows a
rung using a division instruction.
Figure 9-74. Division functional block with the second result register storing (a) the
decimal fraction and (b) the remainder.
Figure 9-73. Ladder format division instruction.
DIVISION—BLOCK
A division (DIV) functional block finds the quotient of two numbers, storing
the result in one or more registers. Figure 9-74 illustrates this type of
functional block. The division calculation begins after the control rung has
continuity. Registe 1000 (the dividend) is divided by the contents of register
1001 (the divisor), and the result is stored in two contiguous destination
Reg: 1000
10
DIV
100
GET
Reg: 1001 Reg: 2000
2001
GET
÷
Integer
Fraction
Reg 1000
÷
Reg 1001
=
Reg 2000
2001
Reg: 1000 = 8527
Reg: 1001 = 325
Remainder
Overflow
Done or
Enable
DIV
Control
Integer result in register 2000 = 26
Decimal fraction in register 2001 = 2369
Result = 26.2369
Integer result in register 2000 = 26
Remainder in register 2001 = 77
Result = 26 with a remainder of 77 (77/325)
(a)
(b)
or
DIV
÷
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The square root instruction is useful in applications like the calculation of
flow rate from a differential pressure (DP) orifice flow meter (see Figure 9-
76). In this application, the flow rate (Q) is equal to a constant (K) times the
square root of the differential pressure (∆P
A
= P
out
– P
in
). The analog input
value from the DP flow meter must have its square root value extracted and
then multiplied by the constant. The resulting value will give the volume per
unit time (ft
3
/min) of the flow. Chapter 13 further discusses differential
pressure transducers and their measurements.
registers. In this case, the destination registers are register 2000, which holds
the integer part of the result, and register 2001, which holds the decimal
fraction part. Depending on the controller, the second result register may hold
the remainder instead of a decimal fraction. Some controllers also allow a
scaling factor to be specified in a division block. This scaling factor permits
fractional results, which would otherwise be lost, to be scaled and stored in
a register.
Depending on the PLC used, a division block can have three possible outputs.
When energized, the top output generally represents a successful division, the
middle output represents an overflow or error (divide by zero), and the lower
output indicates whether or not the result has a remainder.
SQUARE ROOT—BLOCK
Figure 9-75. Square root functional block.
A square root (SQR) block instruction generally has two or three registers—
one that holds the value to be operated on and one or two other registers that
hold the result of the square root operation. One of the result registers may
hold the integer part of the result while the other holds the fractional part. The
processor may also provide scaling. Once the control rung has continuity, the
square root operation takes place. Of the possible block outputs, the first one
represents a successful or valid operation, nd the second one indicates an
overflow condition. Figure 9-75 illustrates a square root block instruction.
Reg 1000
Reg 2000
2001
Reg: 1000 = 120
Square root result = 10.9544
Reg: 2000 = 10 (integer)
Reg: 2001 = 9544 (decimal fraction)
Overflow
Enable
SQR
Control
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9-11 DATA MANIPULATION INSTRUCTIONS
Data manipulation instructions are enhancements of the basic ladder
diagram instruction set. Whereas relay-type instructions are limited to the
control of internal and external outputs based on the status of specific bit
addresses, data manipulation instructions allow multibit operations. Data
manipulation instructions handle operations that take place within one, two,
or more registers. Table 9-8 presents some data manipulation instructions.
Data comparison (CMP) instructions, as the name implies, compare the
values stored in two registers. These instructions are useful when checking
for a proper range of values in the control or data entry section of the
application program. In some controllers, data compariso instructions are
expressed in the basic ladder format, while in other controllers, they are block
instructions. In both formats, they provide three basic data comparisons:
compare equal to, compare greater than, and compare less than. Based on
the results of these comparisons, the processor can turn outputs ON or OFF
and perform other operations.
Figure 9-76. Square root instruction application in a DP flow meter.
DP
Ingredient A
DP
Ingredient B
Mixer
Programmable Controller
–10 to +10
Analog
Input
–10 to +10
Analog
Input
0–10 VDC
Analog
Output
0–10 VDC
Analog
Output
∆
P
A
∆
P
A
Q
A
=
K
A
Q
B
=
K
B
∆
P
B
∆
P
B
To 120 VAC Discrete
Output in PLC
DATA COMPARISONS
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Table 9-8. Data manipulation instructions.
Comparison instructions that use the basic ladder format operate in a manner
similar to arithmetic instructions (see Figure 9-77). If the rung has continuity,
the instruction performs a comparison; if the comparison is TRUE, the
instruction passes continuity to the output coil. Typical comparison instruc-
Figure 9-77. Ladder format comparisons.
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Reg 600
10 100
GET
Reg 501
CMP=
Reg 601
11 101
GET
Reg 502
CMP=
Reg 502
CMP>
If contact 10 closes, the contents of register 600 are compared to the contents
of register 501; if they are equal, coil 100 is turned ON. If contact 11 closes,
the contents of register 601 are compared to the contents of register 502; if
they are greater than or equal to register 502, output 101 is turned ON.
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Figure 9-79. Comparison block using a limit instruction.
Figure 9-78. (a) Single-comparison and (b) multicomparison functional blocks.
tions are greater than (>), less than (<), and equal to (=), along with
combinations of these such as less than or equal to (≤), greater than or equal
to (≥), and not equal to (≠). A GET instruction accesses the first register to be
compared to the comparison (CMP) register. Note that all ladder conditions
are programmed before the GET and CMP instructions.
The compare functional block, shown in Figure 9-78a, compares the contents
of two registers, register 2000 and register 2001, for a specific comparison,
in this case, equal to. The block instruction energizes output coil 100 when the
comparison occurs, and it energizes output coil 101 if the comparison has
been satisfied. As shown in Figure 9-78b, some PLCs may also have one
comparison block, which has several outputs, that performs multiple compare
functions at the same time. This type of comparison block compares the data
in the registers and then turns ON the output corresponding to the outcome of
the comparison (i.e., less than, greater than, equal to).
Some controllers offer another comparison option that uses another register
to perform a limit (LIM) instruction. This instruction compares the values in
three registers to determine if the value in the middle register is between the
other two register values. For example, the limit functional block shown in
Figure 9-79 compares the contents of registers 1100, 1200, and 1300 to
determine whether register 1200 is less than or equal to register 1100 and
102
Reg 2000
Reg 2001
CMP=
100
101
10
Done/
Enable
Comparison
Satisfied
Note: Other comparision functional
block instructions include
CMP>, CMP≥, CMP<,
CMP≤, and CMP≠.
(a)
Reg 1000
Reg 1001
CMP
100
101
10
CMP=
CMP>
CMP<
(b)
Reg 1100
Reg 1200
Reg 1300
LIM
Ouput is ON if condition is satisfied
(Reg 1100 ≥ Reg 1200 ≥ Reg 1300)
100
101
10
Done/Enable
Comparison
Satisfied
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whether register 1200 is greater than or equal to register 1300 (i.e., R1100 ≥
R1200 ≥ R1300). If the comparison is TRUE, the limit instruction energizes
the comparison-satisfied output. The done/enable output is ON whenever the
instruction is enabled.
Some controllers that do not have compare block capabilities can perform a
comparison of two registers using a subtraction block (see Section 9-10). In
this case, three output coils signal whether the result of the subtraction is
positive (greater than), equal (equal to), or negative (less than).
Figure 9-80. Mixing application and its corresponding ladder program.
EXAMPLE 9-9
Figure 9-80 shows a section of the program from Example 9-8 in
which an ADD instruction was used to keep track of the two ingredients
being poured into a reactor tank. The first two ladder rungs open the
valves for ingredients A and B, allowing them to be poured into the tank
once the Start Adding Ingredients
command is ON (input 10). Imple-
ment an instruction block that ensures that the valves close when
ingredient A reaches 500 gallons and ingredient B reaches 750
gallons.
S
OLUTION
Figure 9-81 illustrates the use of two compare instructions that detect
the target ingredient amounts. The outputs of these compare instruc-
tions are used to interlock and break continuity to each of the valve’s
circuits. Note that the values of the ingredient flows (the contents of
registers 1000 and 1001) are compared with two constants (K). Also,
note that the comparison made is greater than or equal to (≥) to avoid
missing the compare (equal) because of a minuscule movement in the
analog input reading.
Ingredient 1 Ingredient 2
Flow A
Reg 1000
Flow B
Reg 1001
Start Adding
Ingredients
10
Valve A
200
Start Adding
Ingredients
10
Valve B
201
100
Reg 1000
+
Reg 1001
=
Reg 2000
ADD
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Figure 9-81. Solution to Example 9-9.
LOGIC MATRIX
A logic matrix functional block performs AND, OR, exclusive-OR, NAND,
NOR, and NOT logic operations on two or more registers (see Chapter 3 for
logic functions). A logic function performed between two registers can be
thought of as a matrix operation of length one, since each operand has one
register. Figure 9-82 shows a typical logic matrix function block. A logic
matrix operation between two registers may be used to mask out certain bits
of the source or original register and then pass only the status of those bits
used in the mask to the result register (see Figure 9-83).
An enabled control input triggers the performance of a logic matrix function
block. The block specifies the type of logic function to be performed, while
the user specifies the registers inside the block. These are generally holding
or storage registers. Referring to Figure 9-82, registers 1000 and 1100 hold
the operand values, while register 2000 holds the result of the operation. The
length of the operation indicates the number of words or registers adjacent to
each of the register operands, providing data in matrix form.
Start Adding
Ingredients
10
Valve A
200
Stop A
102
Start Adding
Ingredients
10
Valve B
201
Stop B
104
100
101
102
Start Adding
Ingredients
10
Reg 1000
+
Reg 1001
=
Reg 2000
Reg 1000
K500
CMP≥
103
104
Start Adding
Ingredients
10
Reg 1001
K750
CMP≥
Enable
Enable
CMP Satisfied
(Ingredient A)
CMP Satisfied
(Ingredient B)