Bryan L. Programmable controllers. Theory and implementation
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8 to 64 or more. The width of the table may also vary, as may the size of a
cylinder. Through I/O registers, which map real output points, each step in a
sequencer table can become an output representing one of the pegs.
Figure 9-111. Comparison of a music box cylinder and a sequencer table.
Figure 9-112 shows a typical sequencer functional block. An OFF-to-ON
transition of the control input initiates this block, causing the contents of the
sequencer table to be output in a sequential manner. The pointer register
points to each step being output (i.e., the table register location). Every time
the control input is energized, the pointer register is automatically
incremented, thus pointing to the next table location. Depending on the PLC,
either an event or time may drive the control input line; therefore, sequencers
may be either event driven or time driven. A reset pointer input can reset the
pointer register to zero (point to step 1), if needed. The sequence length and
width specify how many steps and bits are in the table, respectively. When-
ever the sequencer instruction is enabled, it energizes the block’s first output.
The second output indicates the end of the sequencer table.
Figure 9-112. Sequencer functional block.
1111001100101011
0011000010101000
1100111101010111
0101011000101010
1
1
2
3
4
5 011000111001001
Drum
Table
Steps
1 = Energize
0 = De-energize
Bit locations in table
1
2
3
4
5
Rotation
Cylinder
Steps
Table Reg 1000
Pointer 2000
Length 05
Width 16
Out Reg 3000
10010
SEQ
10120
Control
Reset
Pointer
Enable
End of
SEQ Table
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EXAMPLE 9-12
A PLC application calls for the implementation of ten different steps
that take place in a sequential manner. For the purpose of detecting
a fault in a troubleshooting condition, the process step code, as shown
in Figure 9-113, should be revealed in a seven-segment display to the
operator. Implement an instruction block that will satisfy this application.
Figure 9-113. Process step code.
SOLUTION
Figure 9-114 shows a way to display the code number using a 16-bit
register output connected to a four-digit, seven-segment display. A
sequencer instruction transfers the codes from the sequencer table to
the output register. The output register matches (i.e., is mapped to) the
location of the 16-bit output interface (i.e., rack 0, slot 7, correspond-
ing to word 07). Every time the Start of Process Step signal goes from
OFF to ON, the sequencer will output the process code to the indicator.
Figure 9-114a. Sequencer instruction block.
1023
4576
4588
5101
5130
5417
5418
7809
7810
7900
CodeStep
1
2
3
4
5
6
7
8
9
10
SEQ
400
Start of
Process
Step
Begin
Process
Step 1
Table Reg 1000
Pointer 2000
Length 10
Width 16
Out Reg 07
Control
401
Reset
1023
4576
4588
5101
5130
5417
5418
7809
7810
7900
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
Reg
Storage
Area
Contents in
BCD
Note: The contents of Reg 2000 (the pointer)
are the table register location starting at
1000 (1st location).
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Figure 9-114b. Seven-segment display.
DIAGNOSTICS
A diagnostics (DIAG) block instruction compares two memory blocks, one
containing actual input conditions and the other containing a reference
condition. The instruction compares these blocks bit by bit to determine if
they are identical. If a miscomparison occurs, the instruction stores the bit
number and the state of the bit in a holding register. Diagnostic instructions
are useful for signaling machine malfunctions.
Figure 9-115 illustrates a diagnostic function block. An energized control
input initiates the block function. The block then compares the contents of the
first register locations (1000 through 1007) with the contents of the second
Figure 9-115. Diagnostics functional block.
01234567
101000100111011
001100110101010
010110000111001
101000100111011
001110100101010
111001100110010
101011000111001
001001100100110
1000
1001
1002
1003
1004
1005
1006
1007
Reg
101000100111011
001100110101010
010110000111001
101000110111011
001110100101010
111001100110010
101011000111001
001001100100110
2000
2001
2002
2003
2004
2005
2006
2007
Reg
If a miscomparison occurs,
output 101 will be ON.
DIAG
100
101
10
Ref Reg 1000
Source Reg 2000
Length 08
Reset Reg 3000
Enable/Done
Miscompare
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Figure 9-116. PID functional block.
An energized control input enables a PID block’s automatic operation. The
bottom input track, when energized, determines whether the PID variables are
being tracked but not output. If the block is not enabled (i.e., in manual mode),
the controller can still track the variables when the track line is enabled. The
user specifies the input variable register (IVR) and the output variable register
(OVR), which are associated with the locations of the analog modules (input
and output). The proportional register (PR), integral register (IR), and
derivative register (DR) hold the gain values that must be specified for the
three parts of the control process. The set point register (SPR) holds the target
value for the process set point. Depending on the controller, the user can
specify other block variables, such as dead times, high and low limits, and
rate of update. The top output of the PID block indicates an active loop
reference register locations (2000 through 2007). If it finds a difference, it
stores this information in the result register (register 3000) without altering
the contents of the other register locations. When the instruction is finished,
it energizes the top output. The instruction energizes the second output if a
miscomparison occurs.
The controlled machine generally determines the reference conditions for
inputs and outputs. However, some controllers allow reference conditions to
be “taught” to the PLC. These controllers gather reference teaching condi-
tions using sequencer input, block transfer in, and other instructions, depend-
ing on the model used.
PID
PLCs that are capable of performing analog control using the PID algorithm
use proportional-integral-derivative (PID) functional blocks. The user speci-
fies certain parameters associated with the algorithm to control the process
correctly. Figure 9-116 illustrates a typical PID block.
PID
10010
IVR 110
OVR 120
PR 1000
IR 1001
DR 1002
SPR 2000
Control
15
Track
Register 110 maps analog input module
Register 120 maps analog output module
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Figure 9-117. Fill-in-the-blanks screen.
control, while the middle and bottom outputs indicate low- and high-limit
alarms, respectively. Some PLC manufacturers provide a fill-in-the-blanks
screen (see Figure 9-117) during the programming of a PID instruction, so
that the user can input the different parameters.
Some controllers provide PID capabilities without the PID block instruction.
In this case, the controller uses a special PID module that contains all of the
input/output parameters. An output instruction, such as block transfer out or
move data, transfers the set point and gain parameters to the module during
initialization of the program. The control program can alter this module data
if any parameter changes are required. Chapter 15, which explains process
controllers and loop tuning, provides more information about PID control.
9-14 NETWORK COMMUNICATION INSTRUCTIONS
Local area networks (LANs) provide communication channels between
independent computers (referred to as nodes) located in a small radius.
Because they connect different computers, LANs have created a need for
instructions that communicate and exchange information between the PLCs
in a network. Therefore, PLC manufacturers now offer network communi-
cation instructions, which transfer information like contact status, output
coil status, and register status between PLCs. These network instructions are
often specific to the manufacturer’s family of PLCs.
Table 9-11 describes typical instructions used in a PLC network environ-
ment. These instructions are very easy to implement; however, the program-
mer must enforce compliance with the PLC network’s rules. Also, the
programmer should assign registers and organize the program to avoid
confusion on the network.
PID LOOP# (1-64) TITLE: (8 charac.)
PID LOGORITHM: (Position or Velocity)
LOOP FLAG ADDRESS: (WY, V, C, NONE)
PROCESS VARIABLE ADDRESS: (WX, WY, V)
SQUARE ROOT OF PV? (Yes or No)
PV RANGE: HIGH: (Eng. Units)
LOW: (Eng. Units)
SAMPLE RATE: (0.1 to 6553.5 secs)
DERIVATIVE GAIN LIMITING
COEFFICIENT. . . (Eng. Units)
SPECIAL CALCULATION ON: (PV or SP)
SFPGM NUMBER
RAMP/SOAK FOR SP (Yes or No, Yes forces Remote Setpoint to No)
REMOTE SETPOINT? (Yes or No)
CLAMP SETPOINT LIMITS: HIGH: (Eng. Units or No entry)
LOW: (Eng. Units or No entry)
ERROR OPERATION: (Squared, Deadband, None)
LOCK SP? (Yes /No)
LOCK AUTO/MANUAL? (Yes /No)
LOCK CASCADE? (Yes /No)
PV IS BIPOLAR? (Yes /No)
20% OFFSET? (Yes /No)
PERFORM DERIVATIVE
GAIN LIMITING. . . (Yes /No)
REMOTE SP ADDRESS: (WX, WY, V, or K)
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Table 9-11. Network communication instructions.
Once a PLC executes a network communication instruction and updates it at
the EOS, the processor passes the information to the network hardware
(modules or internal boards) for processing and transmission. The format of
the instruction may differ, depending on the controller—some controllers use
data transfer instructions to access the network, while others use specific
instructions. Therefore, the instructions presented here are guidelines to
illustrate implementation.
The organization of a network depends on how it is configured. In some
controllers, the network interface is built into the main CPU, while in others,
it is in an interface module. Regardless of format, both network interfaces
perform the same function—network communications. If a PLC’s network
interface is installed in the I/O racks, the manufacturer may provide one of a
number of ways to set up that particular PLC for the network. Some PLCs may
configure the network during the configuration stage, when the network
module slot location is specified. Other controllers may automatically recog-
nize where the network interface is located. Yet in other PLCs, a network
software instruction, similar to a block transfer in or block transfer out
instruction, specifies the network module’s slot location.
The output coils and contacts in a network may be referred to as network
outputs and network contacts, while the registers in a network may be called
network registers. Network outputs are internal outputs that are often located
in a special area of the data table, along with the network registers. These
network elements may be part of an internal storage area with additional LAN
capabilities. For example (see Figure 9-118), if a PLC has 512 possible
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NET
ZCL
NET
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internal outputs, 64 of them may be used as network outputs; likewise, if it has
128 storage registers, 32 of them may be used as network registers. These
network-mapped addresses, if used, will be sent automatically if the network
is active. Chapter 18 explains local area network operation and configuration
more extensively.
Figure 9-118. Mapping of network-compatible addresses with all numbers in octal.
Now, let’s explore the operational function of some network instructions. In
this discussion, we will assume that the programmable controller specifies
the slot location of the network interface during the total system configura-
tion. If this was not the case, then the PLC would require a slot entry
specification for each instruction.
NETWORK OUTPUT
A network output instruction, shown in Figure 9-119, is used in conjunction
with a network contact to pass one-bit status information from a PLC to the
network. If continuity exists in the logic path of the network output, the
network output instruction will turn ON its corresponding reference address.
It will then send the information about the status of the reference address to
the network interface for LAN transmission. Depending on the controller, the
reference address must be a valid network coil. After transmission, the status
of the output is available to all network stations or nodes (PLCs).
171615141312111076543210
0000
0037
0040
0043
0077
R0277
R0100
R0137
64 compatible
internal outputs with
network addresses
4000 through 4317
171615141312111076543210
32 compatible
storage registers
with network
addresses R0100
through R0137
512
Real I/O
512
Internals
128
Storage
Registers
ZCL
NET
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NETWORK CONTACT
A network contact instruction captures the status information from a network
output. The reference address of the network contact must be the same as that
of an active network output; otherwise, the contact (examine ON or examine
OFF) will never be evaluated. The reference must also be a valid reference
address, which may differ among PLC manufacturers.
Figure 9-119 illustrated the operation of a network contact instruction used
in conjunction with a network output instruction. In this instruction, the
processor obtains information from the network as it reads the inputs, during
which it reads the status buffer of the network module as though it were a small
data table. If the referenced network output address is logic 1, the controller
will perform an evaluation and open or close the referenced contacts to
provide or remove continuity. This evaluation depends on how the network
contact is programmed (normally open or normally closed).
Figure 9-119. Operation of a network output coil and a network contact instructions.
Note that contact 20 in PLC #2 is a local contact.
A network send (NET SEND) instruction sends register information to a
local area network. The activation of this functional block is the same as for
other blocks—if the rung is TRUE, then the instruction is performed, sending
NETWORK SEND
Net 10010 12 300Net 100
20
Coil
Net 100 = 0
Contacts
Net 100
Open
Net 10010 12 300Net 100
20
Coil
Net 100 = 1
Contacts
Net 100
Closed
At the EOS, the
processor sends
the status of all
network coils used
in PLC #1.
PLC #1 PLC #2
During the read section
of the scan, the proces-
sor of PLC #2 reads the
status of all network out-
puts and uses this data
in its program.
LBL
NET
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the contents of the register to the network line. The instruction may provide
two outputs to indicate that the operation has been performed and that no
error was detected (output 1 and output 2, respectively).
Figure 9-120 illustrates a typical network send instruction block. If the
specified length is more than one, the network may receive several transmit-
ted registers; the registers to be transmitted will start at the first register and
end at last register (first + length). A network send instruction generally
operates in conjunction with a network receive instruction.
Figure 9-120. (a) Network send and (b) network receive instructions.
NETWORK RECEIVE
A network receive (NET RCV) block function captures the available
registers in the network’s lines and stores their information in the receiving
PLC’s data table (register area). The user must make sure that the register
information requested (i.e., register address numbers) matches the addresses
used by the NET SEND instructions. For instance, if a NET SEND
instruction uses network registers 400 to 403 (length of 4), the PLC that
will retrieve those network registers must reference the same network
registers in its NET RCV instructions.
Figure 9-120 illustrated the use of a network receive instruction. Once a
network instruction captures the register information, it stores the data in the
destination register(s), as specified by the length of the block. Of the two
outputs available, the first one represents the completion of the operation,
while the second one indicates if an error has occurred.
PLC #1 PLC #2
NET SEND
10010
Reg 400
Length 04
NET RCV
200
101 201
20
Reg 400
Length 04
Dest
Reg 1000
The contents of network
registers 400 through 403
(length = 4) are sent to the
network at EOS.
The contents of network registers
400 through 403 are received by
PLC #2 and stored in registers
1000–1003.
(a) (b)
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Figure 9-121. Send node functional block operation.
SEND NODE
A send node (SEND NODE) instruction operates in a more direct way than
a network send function. This instruction transmits register information to
specific PLCs (nodes) connected to the network. Essentially, a send node
function implements a copy to function, where several registers from the
sending node are written to another node.
Figure 9-121 illustrates a send node instruction. Continuity in the
instruction’s control line enables the block, which sends the contents of the
starting register through the last register to the specified node. The block
stores the information from the starting register through the last one in
destination registers. The completion of the instruction turns ON the first
output, while a network error condition energizes the second output.
GET NODE
A get node (GET NODE) instruction retrieves register information from
another PLC node. This instruction essentially copies the register from the
requested node to the requesting node.
Figure 9-122 illustrates the use of a get node function. When the block is
enabled, it requests the contents of the specified registers in the target node
and stores the data in the destination registers of the PLC executing the get
PLC #1 PLC #2
Send Node
100
Enable/Done
10
Reg 400
Length 01
To Node 10
Reg 1000
101
Error
The contents of network register
400 are sent (written) to register
1000 of the PLC with node address
10 (PLC #2).
Reg 400 Reg 1000
Node 05 Node 10